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Timing Driven, Congestion Aware Reconfiguration of Scan Chains

IP.com Disclosure Number: IPCOM000198377D
Publication Date: 2010-Aug-05
Document File: 4 page(s) / 155K

Publishing Venue

The IP.com Prior Art Database

Abstract

Abstract—: Scan chains used for scanning in data during testing are most susceptible to hold violations resulting in loss of data. Problem increases many fold with performance de-ration due to On Chip Variation (OCV). It is a major concern because OCV targets are becoming more stringent with shrinking technology where apart variation in routing topology also plays a prominent role apart from defects in device fabrication. This paper explains a novel method of reordering scan chains, which will ensure that hold violations occurring due to variation in cell as well as net delay in a chip are minimized. Thus buffer insertion during hold fixing will be reduced to a great extent which will mean power and area saving. The method will further ensure that routability issues due to reordering are minimized by taking net length variable into account. Also hold violations seen in best corner and worst corner are minimized regardless of whether OCV is there or not. This method makes use of the clock tree structure to reorder the scan chains in such a way that the common clock path between each pair of flops is maximized. Doing this makes the scan chain OCV aware with minimum design overhead. It ensures that sanctity of the scan chain is maintained in terms of scan chain length, scan chain number and test clock domain. The method further ensures that negative skew is implemented between all flops, with a few exceptions, to reduce their hold criticality.

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Timing Driven, Congestion Aware Reconfiguration of Scan Chains

Abstract: Scan chains used for scanning in data during testing are most susceptible to hold violations resulting in loss of data. Problem increases many fold with performance de-ration due to On Chip Variation (OCV). It is a major concern because OCV targets are becoming more stringent with shrinking technology where apart variation in routing topology also plays a prominent role apart from defects in device fabrication. This paper explains a novel method of reordering scan chains, which will ensure that hold violations occurring due to variation in cell as well as net delay in a chip are minimized. Thus buffer insertion during hold fixing will be reduced to a great extent which will mean power and area saving. The method will further ensure that routability issues due to reordering are minimized by taking net length variable into account. Also hold violations seen in best corner and worst corner are minimized regardless of whether OCV is there or not. This method makes use of the clock tree structure to reorder the scan chains in such a way that the common clock path between each pair of flops is maximized. Doing this makes the scan chain OCV aware with minimum design overhead. It ensures that sanctity of the scan chain is maintained in terms of scan chain length, scan chain number and test clock domain. The method further ensures that negative skew is implemented between all flops, with a few exceptions, to reduce their hold criticality.

                   I.  Introduction

In VLSI design, there is an increased emphasis on testability. Besides satisfying the intended functional requirements, the System-on-Chip (SoC) must be testable and should have optimum test-coverage. Testing, broadly defined, has two steps. In the first step; the design has to be taken to a known state. In second step, the design in the known state is tested functionally and the output is compared to an expected output to verify the functionality. Different methods and architectures are available to achieve this end. For taking the design to a known state, one of the available methods is to directly shift in data through a chain consisting of flops only. The flops are connected like a shift register and known data is scanned-in to each flop bitwise. Such chains are called scan-chains. Fig 1 shows one such scan chain.

Fig 1: Q to Sdi Path in a Scan Chain

The hold time of a flip flop is defined as the minimum time for which the data input must be stable after the capture edge of the clock pulse. If the data toggles before the appropriate edge of the clock pulse arrives, then a hold violation will arise. This will lead to the data being fed through two flops in the same clock cycle. It may cause meta-stability as well. In scan chains output of one flop is directly connected to scan input of another flop. Thus scan paths have very little propagation delay making them hold time critical.

Depending on the way clock tree is built, i...