Method and Structure for Forming System-On-Chip Including High-Performance Device and Low-Power Device
Publication Date: 2010-Aug-10
The IP.com Prior Art Database
This invention provides a method and structure for integrating various devices on the same chip in system-on-chip technology. Core approaches to improving current processes include: forming SONOS flash memory and logic FET on the same chip, forming floating gate flash memory and logic FET on the same chip, forming a recessed channel DRAM and logic FET on the same chip, and forming a decoy device or Depletion Mode FET and logic FET on the same chip.
Method and Structure for Forming System -On-Chip Including High-Performance Device
and Low-Power Device
The advance of semiconductor technology requires continued shrinkage of device
dimension and integration of devices with various functions on the same chip. For
example, a system-on-chip (SoC) typically includes high-performance logic devices,
low-power memory devices, and passive devices such as capacitors and resistors. One of the challenges here is that different devices have different characteristic
requirements: logic devices usually have very aggressively shrunk gate length for
high-performance; whereas, small gate length devices may not be suitable for memory
application due to excessive leakage current. Using long channel devices suppresses
leakage current, but such an approach is at the cost of low device density which
contradicts the high-density requirement of memory application.
Another challenge of fabricating SoC is that different devices have different gate stacks.
For example, the gate stack of a flash memory device can be dramatically different from
the conventional logic of field-effect transistor (FET). A flash memory device typically
comprises more layers, including the control gate layer, charge barrier layer, floating
gate layer, and tunneling dielectric layer. In contrast, a logic FET gate stack comprises
a gate dielectric and a gate conductor. Having different gate stacks poses severe
challenges in gate patterning. Separate processes, some of which may not even be
compatible with standard complementary metal-oxide semiconductor (CMOS)
processes, form the different types of devices. Consequently, known approaches have
several drawbacks such as process complexity, increased cost, etc.
Disclosed is a solution for improving the methods for integrating various devices on the
same chip. The key process steps are described in the typical embodiments. Compared
with prior art, this method has following advantages.
• Independent tunability of gate stack for different devices
• Excellent compatibility with standard CMOS
Embodiment #1: Forming SONOS flash memory and logic FET on the same chip
A. Requires that a logic FET and a non-logic FET (DRAM, flash, resistors, etc.) are
first formed by standard CMOS process well known in the art. Each device
comprises a gate, channel, and source/drain. Spacers are also formed on gate
sidewalls. An inter-layer dielectric (ILD) (e.g., oxide) is deposited and planarized.
B. Uses a block mask to expose the non-logic device. The exposed gate of the
non-logic device is then removed by etch. For example, when the original gate
comprises polysilicon and silicon oxide, a wet etch containing ammonia can be
used to remove polysilicon and hydrofluoric acid can be used to remove gate
C. Removes the gate in the non-logic region to expose a channel of non-logic
devices. In some embodiments, the channel is recessed to increase gate length
to suppress leakage cur...