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Method and System for Improving Single Event Upset (SEU) Capability of Bulk Silicon Semiconductors

IP.com Disclosure Number: IPCOM000198591D
Publication Date: 2010-Aug-10
Document File: 2 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for improving Single Event Upset (SEU) capability of bulk silicon semiconductors is disclosed. Charge collection centers are provided in the bulk silicon semiconductors by incorporating specific amount of metals into a silicon substrate without contaminating an active device.

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Method and System for Improving Single Event Upset (SEU) Capability of Bulk Silicon Semiconductors

Disclosed is a method and system for improving Single Event Upset (SEU) capability of bulk silicon semiconductors. Charge collection centers are provided in bulk silicon semiconductors by incorporating specific amount of metals into a silicon substrate without contaminating an active device. The charge collection centers formed into the silicon substrate are capable of collecting the radiation transmitted through the silicon substrate. As a result, the probability of cosmic rays and decomposition particles from striking the active device are minimized.

Fig. 1 illustrates a fabricating process for improving the SEU capability of bulk silicon semiconductors.

Figure 1

A p+ or p- type of substrate is used for growing a silicon boule using a standard formation process having oxygen content greater than 30ppm. Thereafter, in step 2 the substrate undergoes nucleation process for creating silicon defects in the substrate by growing oxygen-precipitates in the center of the substrate. The nucleation process is carried in such a way that the surface of the substrate remains a denuded zone that is free from oxygen precipitates. In an instance, p+ type doped substrate may be grown over the denuded p+ type substrate surface for additional latch-up and SEU immunity. Subsequently, p- type epitaxial silicon is grown over the denuded p+ type substrate surface. As shown in Fig. 1, in step 3, Complementary Metal-Oxide-Semiconductor (CMOS) devices (for example transistors or latches) and multi-level metal wirings are...