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Circuit and Methodology for Stressing Transistors for NBTI and TDDB and Differentiating the Circuit Effects of NBTI and TDDB

IP.com Disclosure Number: IPCOM000198592D
Publication Date: 2010-Aug-10
Document File: 6 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an invention which teaches a circuit and methodology for stressing Negative Bias Temperature Instability (NBTI) and Time-Dependent Dielectric Breakdown (TDDB) either separately or together within a Ring Oscillator (RO) circuit. This allows testers to observe the circuit impact of the shifts together if a severe stress is applied such that the device experiences both NBTI and TDDB.

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Circuit and Methodology for Stressing Transistors for NBTI and TDDB and

Differentiating the Circuit Effects of NBTI and TDDB

As technology progresses and the dimensions continue to shrink, Negative Bias Temperature Instability (NBTI) and Time-Dependent Dielectric Breakdown (TDDB) interact to cause circuit failure in a complex way. Dielectric breakdown is no longer a single hard event for the thinner oxides, but rather a growth event causing slowly increasing gate currents while NBTI is slowly causing threshold voltage shifts.

At present there is no known way to experimentally separate the impact of these effects on a circuit. It is important for the modeling to be able to separate these effects to know their relative contributions to the circuit degradation.

Today, testers stress devices separately for NBTI and TDDB at a test site level and compare them to results from SRAM stressing. But the various contributions can only be inferred and not directly measured.

This invention teaches a circuit and methodology for stressing NBTI and TDDB either separately or together within a Ring Oscillator (RO) circuit. Because of this ability, testers can observe the circuit impact of the shifts together if a severe stress is applied such that the device experiences both NBTI and TDDB. Another RO could be stressed at conditions that cause only NBTI, and those circuit impacts observed. Furthermore testers can independently measure both Vt and IG of the Device Under Test (DUT), as well as stress and measure both the pmos device and nmos device.

Figure 1 represents one cell of this Ring Oscillator. The RO pair are highlighted, the rest of the circuitry is support circuitry.

A scan chain controls the state of each cell. This means that all of the cells can be in the same state or one cell can be in the opposite state from all of the remaining cells, or any configuration between those two extremes.

If the scan chain signal is such that its output flip-flop signal is low, then the following occurs:

The transfer gates going to each of the pads is off

The transfer gate connecting the pfet drain to Vdd is on

The transfer gates connecting the gates to the input signal A are on

The transfer gates interconnecting the RO nfet and pfet and the output Y are on

The transfer gate connecting the nfet source to gnd is on

Hence in this condition the cell is a simple RO stage with input A and output Y.

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If the scan chain signal is such that its output flip-flop signal is high, then the following occurs:

The transfer gates going to each of the pads is on

The transfer gate connecting the pfet drain to Vdd is off

The transfer gates connecting the gates to the input signal A are off

The transfer gates interconnecting the RO nfet and pfet and the output Y are off

The transfer gate connecting the nfet source to gnd is off

Hence in this condition the RO nfet and pfet are removed from the RO circuit and each transistor termi...