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Improved Method of Determining Subthreshold Current During Active Circuit Operation

IP.com Disclosure Number: IPCOM000198593D
Publication Date: 2010-Aug-10
Document File: 2 page(s) / 31K

Publishing Venue

The IP.com Prior Art Database


This disclosure shows that for Silicon-on-Insulator (SOI) technologies the leakage power in quiescence is not identical to that in active mode, due to the history effect. Described is a methodology for appropriately adjusting the calculations to correctly accommodate both modes of operation.

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Improved Method of Determining Subthreshold Current During Active Circuit Operation

Leakage in quiescent mode is important for standby applications, but in high-performance chips the leakage component of power in the active mode is of paramount significance as well. Calculating both of these is very important. Timing and power models usually contain switching and leakage of power information.

There should be at least two leakage entries: one for quiescence and one for when switching occurs. The same number does not, in principle, apply for both modes of operation; both of which are important to chip design and circuit operation.

The power information is derived in one of two ways: by circuit simulation or by spreadsheet calculation.

Circuit simulation method:

1. Define quiescent current with a DC simulation in the appropriate logic state or states; termed Idd

_quiescent with no switching taking place

2. Define leakage-in-active with a transient simulation at various frequencies. Extrapolate to zero frequency; termed Idd

_active, which is not the same in

quiescent is found to be 1.39uA

                  active is 1.91uA when switching is taking place, a 37% increase in leakage power.

Figure 1: Circuit simulation method




general as Iddq.

Figure 1 shows (45SOI, rvt device at 0.9V) where Idd

for this circuit, and Id



[This page contains 1 picture or other non-text object]

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In principle, there may be different leakage entries for different frequencies, but th...