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Flexible NAND Flash Memory Controller Design

IP.com Disclosure Number: IPCOM000199023D
Publication Date: 2010-Aug-23
Document File: 4 page(s) / 387K

Publishing Venue

The IP.com Prior Art Database

Abstract

NAND Flash memory is a non volatile memory which is used in variety of applications like MP3, code storage, cell phone, digital camera etc. NAND Flash is command based memory, hence no dedicated address bus is required. It is accessed through command, address and data phases. Different vendors support different commands and timing at the NAND memory interface. No single standard is available. In this paper we are going to explain the Flexible NAND Flash Memory Controller design, which is used to interface with multiple NAND devices supporting different interface timings and command sets. We will describe the various components and their functionality in detail.

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Flexible NAND Flash Memory Controller Design

Abstract— NAND Flash memory is a non volatile memory which is used in variety of applications like MP3, code storage, cell phone, digital camera etc. NAND Flash is command based memory, hence no dedicated address bus is required. It is accessed through command, address and data phases. Different vendors support different commands and timing at the NAND memory interface. No single standard is available. In this paper we are going to explain the Flexible NAND Flash Memory Controller design, which is used to interface with multiple NAND devices supporting different interface timings and command sets. We will describe the various components and their functionality in detail. 

I.     INTRODUCTION

N

AND technology provides a cost-effective solution for applications requiring high density solid-state storage. NAND Flash devices use a highly multiplexed 8- or 16-bit bus (I/O[7:0] or I/O[15:0]) to transfer data, addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#) implement the NAND command bus interface protocol. Three additional pins control hardware write protection (WP#), monitor device status (R/B#), and initiate the auto-read feature (PRE—3V device only). This hardware interface creates a low-pin-count device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities without board redesign. The NAND Flash devices, for e.g. could contain 2,048 and 4,096 erasable blocks respectively. Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes (x8) or 1,056 words (x16). The pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, separate 1,024-word and 32-word areas. The 64-byte and 32-word areas are typically used for error management functions. The contents of each 2,112-byte page can be programmed in approximately 300μs, and an entire 132Kbyte/ 66K word block could be erased in 2ms. On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. ERASE/PROGRAM endurance is specified at around 100,000 cycles when using appropriate error correcting code (ECC) and error management.

The NAND Flash Controller described in this paper  provides flexibility in terms of generating programmable timing at the interface as well as by supporting different command sets supported by various NAND vendors. NAND Flash controller contains an instruction sequencer which executes the instruction opcodes programmed by the user in the registers and generates the commands and timings as per the values programmed in the command and timing registers.

II.     Architecture

Figure 1describes the design details of the Flexible NAND Flash Controller. It has the following sub-blocks:

1.   System Interface: It communicates with the system bus and controls the transfer of the data/address between SRAM buffer and system bus.

2.   Re...