Browse Prior Art Database

Method and System for Speeding a Hardware Stress Test

IP.com Disclosure Number: IPCOM000199065D
Publication Date: 2010-Aug-25
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for speeding a hardware stress test is disclosed. The hardware stress test is accelerated using swarm intelligence to modify a test pattern in real-time. Using this method, high system performance is achieved at a much faster rate and more accurately.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Method and System for Speeding a Hardware Stress Test

Disclosed is a method and system for speeding a hardware stress test. The hardware stress test is accelerated using swarm intelligence to modify a test pattern in real-time.

Fig. 1 illustrates a typical test set-up for performing a hardware stress test.

Figure 1

As depicted in fig. 1, an HTX test tool suite is used to verify PowerPC* hardware design. Hardware Systems Test (HST), I/O Verification (IOV) and Manufacturing use HTX test tool suite to stress test a computer system by exercising all hardware components concurrently. This stress testing of the computer system helps in uncovering any hardware interaction problems or design flaws that went undetected earlier. In addition to using HTX test tool, as part of the stress testing, HTX 64 bit memory exerciser is used as an input to perform the memory testing. HTX 64 bit memory exerciser fills the shared memory segments with a specified bit pattern either by copying from an internal memory buffer (using 1 byte, 4 byte or 8 byte stores) or by reading from a pattern file.

At present, the specified bit patterns used by HTX 64 bit memory exerciser are zeros, Hex Fives and Hex AAs. In addition, these patterns are repeated in a cyclic fashion for 'x' number of iterations wherein a hardware test engineer defines the number of iterations as shown below:

write out all zeros to memory; write out all HEX(FF)'s to memory; write out all HEX(55)'s to memory; write out all HEX(AA)'s to memory.

However, as shown in fig. 1, HTX 64 bit memory exerciser randomly writes different bit patterns or input with no previous knowledge of the performance or output. Thus,

1

[This page contains 1 picture or other non-text object]

Page 2 of 3

without previous knowledge of the amount of stress provided by the input, a sustainable performance goal may not be achieved.

Therefore, in order to overcome this problem, the method optimizes the testing methodology described earlier to achieve optimal stress performance in minimal time. To this end, along with random inputs, swarm intelligence optimization is used wherein the bit pattern is considered to be in swarm and the bit pattern is altered from one set to another resulting in higher stress. In addition, along with swarm intelligence, performance measurement counters are used to zero into the right bit patterns to sustai...