Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

A Bit Line Topology That Enables Column Selection for 8T SRAM

IP.com Disclosure Number: IPCOM000199084D
Publication Date: 2010-Aug-25
Document File: 3 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention enables column selection in eight transistor (8T) SRAM. Chang et al. originally proposed 8T SRAM to improve variability tolerance and low-voltage operation of SRAM.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

A Bit Line Topology That Enables Column Selection for 8T SRAM

As disclosed by Chang et al. (1), eight transistor (8T) static random access memory (SRAM) had an additional constraint imposed relative to traditional 6T SRAM. Every cell along a word line had to be written during a write operation. Writing only a fraction of the memory cells connected to word line, what is known in the art as "column selection," was prohibited to realize compact 8T SRAM cells that offered stable operation at extremely low voltage. Write data for every write-selected memory cell had to be presented to this 8T SRAM memory.

The solution presented here overcomes such a limitation with a circuit topology which generates all the necessary write data.

Figure 1 shows a novel bit line topology that connects a representative 8T SRAM cell having three bit line ports to a two port read-write circuit: (2)

1. True write bit line (WBLT),

2. Complement write bit line (WBLC),

3. Read bit line (RBL)

These are connected via a true bit line BLT and a complement bit line BLC. While WBLT and RBL ports of the representative 8T SRAM cell are shown shunted to BLT in the figure, they may also be shunted to BLC instead. To form symmetric circuit bit lines BLT and BLC, half of the 8T SRAM cells may have their WBLTs and RBLs connected to BLTs while the other half may have their WBLTs and RBLs connected to BLCs.

Figure 1: Bit line topology connecting a representative 8T SRAM cell having three bit line ports

1

Page 2 of 3

This invention enables a fractional write or, in other words, column selection. A read-modify-write access may be completed on the bit lines BLT and BLC with the aid of the read-write circuit. In standby, the precharge-not (PREN) input is held low keeping BLT and BLC precharged high.

In either a read or a write operation, the method is as follows:

1. Enable read word line (RWLn) in order to read the datum onto the true bit line BLT.

2. Enable enable-complement-copy (ENC)...