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Method is Disclosed for Fabricating Laterally Diffused Metal Oxide Semiconductor (LDMOS) Device with Oxide Protection Layer Over Drift Region

IP.com Disclosure Number: IPCOM000199574D
Publication Date: 2010-Sep-09
Document File: 5 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for fabricating a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device with oxide protection layer over drift region.

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Method is Disclosed for Fabricating Laterally Diffused Metal Oxide Semiconductor

Method is Disclosed for Fabricating Laterally Diffused Metal Oxide SemiconductorMethod is Disclosed for Fabricating Laterally Diffused Metal Oxide Semiconductor

(

(((LDMOS

LDMOSLDMOS

LDMOS)

))

when the LDMOS device is fabricated

on same wafer as other FETs which have multiple spacer integration schemes, this approach requires more than one additional mask over base process.

The method and structure described herein protects the drift region from spacer etches

with single mask step. An LDMOS device is shown in the following figures where an

oxide is deposited over the FET before any spacer etches are done. The oxide is removed from the LDMOS source and other FETs by a wet etch, taking advantage of the differential etch rates of thermal vs. deposited oxide. With this thick oxide remaining over the LDMOS drift region, FET integration and spacer etching may proceed normally without damage to the drift region silicon/oxide interface. The fabrication steps are shown using the following figures.

Device with Oxide Protection Layer Over Drift Region

A method is disclosed for fabricating a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device with oxide protection layer over drift region.

An LDMOS device is used for high voltage applications such as display drivers and RF amplifiers. An LDMOS device is a lateral structure where an unsilicided, low-doped drift region on drain side transistor drops high drain voltage so full Vds is not placed across gated region.

Quality of silicon/dielectric interface in drift region is required to be good so as not to provide trap states for electrons transiting the drift region under high electric field. There are several ways to insure that the silicon/dielectric interface is high quality, but generally, the silicon also should have a good quality oxide that is protected from spacer etches.

Conv...