Browse Prior Art Database

Reliable Zero Cost Vertical Parallel Plate Capacitor Fabrication Disclosure Number: IPCOM000199575D
Publication Date: 2010-Sep-09
Document File: 5 page(s) / 257K

Publishing Venue

The Prior Art Database


Integration of low-cost and high performance passive capacitors into existing Silicon CMOS technologies is essential for analog and radio frequency (RF) IC applications. Recently, BEOL vertical parallel plate capacitors (VPP) with stacked via-comb structures have emerged as an attractive option due to their low-cost, high density, highly symmetric configurations, and extremely small voltage and temperature coefficients. However, with the scaling of CMOS technology and the adoption of new low-k materials, reliability of such capacitor rapidly becomes a great concern. As a result, it is necessary to invent new VPP structures such that its reliability risk is minimized while its performance is preserved. Two new methods of designing VPP with improved reliability are disclosed in this publication.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 5

Reliable Zero Cost Vertical Parallel Plate Capacitor Fabrication

Reliable Zero Cost Vertical Parallel Plate Capacitor FabricationReliable Zero Cost Vertical Parallel Plate Capacitor Fabrication

Disclosed are two novel methods for making reliable VPP with zero cost.

TDDB is commonly considered as an important reliability issue for VPP within new technologies because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO2

dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. Figures 1 and 2 show a prior art design of VPP with a 3D view and a top-down view. Due to the post-processed blown out vias, a significant line edge irregularity was observed for VPP devices, which effectively induced a worst-case line edge bump effect. As a consequence, low-k TDDB reliability could be severely impacted as shown in Figures 3 and 4. Both TDDB Weibull distribution shape factor and time to breakdown could be significantly reduced as compared to no bump (no via case). Such rough line sidewall bumps will result in many localized high field regions and subsequently enhance the electron injection from cathode to anode during the VPP operation. The electric field concentration at the convex edge along the interconnect trench sidewall could enhance the electron conduction and therefore generate more Cu ions at those local regions. Under a stronger local electric field, they can move and accumulate quickly and easily. Therefore, Cu may be injected more readily, but field assisted diffusion would be reduced accordingly. If the injection of Cu is most important, a serious degradation of low-kTDDB would occur. This simple geometry and field interaction strongly depends on the curvature and density of line-edge bumps.



V3 M3

V2 M2

V1 M1










Page 2 of 5

Fig. 1 F...