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Extension of binary LDPC decoder to non-binary LDPC decoder

IP.com Disclosure Number: IPCOM000199609D
Publication Date: 2010-Sep-13

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The IP.com Prior Art Database

Abstract

In this paper, we show how our recent work on the binary decoder architecture can be extended for GF(q) LDPC codes. We show that the data flow graph at the higher level abstraction remains the same as binary decoder. For this, we will make use of the value reuse properties for Extended Min-Sum (EMS) decoding, recently proposed by Declercq and Fossorier. We also extend the above properties for Min-Max decoding which is similar to EMS.

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Value-Reuse Properties of Min-Sum for GF(q)

1

Department of ECE, Texas A&M University, College Station, TX-77843

1Department of ECE, University of Oklahoma, Norman, OK-73109

  Abstract-In this paper, we show how our recent work on the binary decoder architecture can be extended for GF(q) LDPC codes. We show that the data flow graph at the higher level abstraction remains the same as binary decoder. For this, we will make use of the value reuse properties for Extended Min-Sum (EMS) decoding, recently proposed by Declercq and Fossorier. We also extend the above properties for Min-Max decoding which is similar to EMS.

  Index Terms-low-density parity-check (LDPC) codes, non-binary LDPC, offset min-sum, scaled min-sum, vector processing, decoder architecture, layered decoding, turbo decoding message passing, array LDPC, quasi-cyclic LDPC, Block LDPC, irregular LDPC, IEEE 802.16e, WiMax, IEEE 802.11n, Wi-fi, on-the-fly computation, block-serial processing.

I. INTRODUCTION

 Low-density parity-check (LDPC) codes and turbo codes are among the best known codes that operate near the Shannon limit. When compared to the decoding of turbo codes, LDPC decoders require simpler computational processing, and they are more suitable for parallelization and low complexity implementation. LDPC codes are considered for error correction coding in virtually all next generation communication systems. In [1-5], we proposed memory and logic efficient hardware architectures and dataflow graphs for non-layered decoding and layered decoding for the binary LDPC codes. Non-binary LDPC codes achieve additional gains compared to binary LDPC codes.

 Our work [1-5] introduced the following concepts to LDPC decoder implementation: Block serial scheduling, Value-reuse, Scheduling of layered processing, Out-of-order block processing, Master-slave router, Dynamic state. All these concepts are termed as On-the-fly computation as the core of these concepts is based on minimizing memory and re-computations by employing just-in-time scheduling. This paper shows how our recent work is applicable for non-binary LDPC codes by making use of reduced complexity check node update algorithms EMS[6-7] and Min-Max [8].

 The rest of the paper is organized as follows. Section II summarizes the EMS algorithm and its properties. Section III further simplifies processing and memory requirements based on min-max algorithm. Section IV extends the binary decoder architectures for GF(q) decoding. Section V makes use of EMS algorithm to simplify check node partial state processing and R select processing. Section VI makes use of the min-max algorithm simplifications.

II. EMS ALGORITHM AND ITS PROPERTIES

Since we use the decoding algorithm from [6-7], we directly make use of the same equations and notations. We will introduce additional notations and equations to facilitate the intermediate calculations in the algorithm detailed in Section 3 of [7]. So to be able to go over this paper, it is a prereq...