Method for reducing switching activity of correlated latches
Publication Date: 2010-Sep-14
The IP.com Prior Art Database
A method is described for finding groups of latches with similar behavior and modify the design such that switching activity of the latches in those groups, and consequently dynamic power, is reduced. The changes introduced into the circuit preserve functional equivalence. The core idea of the method is to identify a dominator latch in each correlated group, which is used to control whether the other latches in the group need to load new values or retain their current values. In particular, the controlled latches load values only when in the original design they behave differently than the dominator. In the presence of high correlation between the dominator and the controlled latches, the controlled latches do not switch most of the time, and thus consume less power.
Power is one of the most important design considerations. Power becomes an even greater problem in modern designs as power consumption does not scale down at the same rate as increase in number of transistors.
A major factor in power
consumption is dynamic power which is caused by capacitors charge and discharge events,
which correspond with toggling of signals,
also known as switching. Hence by reducing switching activity of signals/gates, dynamic power consumption is also reduced. Memory elements, i.e. latches/flip flop, are usually one of the major power consumers, thus they embody large potential for power reduction by reducing their switching activity.
Design methodologies of high-performance processors/systems usually restrict the amount of change allowed by synthesis tools. In particular, a synthesis tool may not add or remove latches/flip flops during the synthesis process. This helps, among other things, for debugging synthesized models and verifying them against the RTL representation. Thus the problem is to reduce switching activity of latches/flip flops without adding or removing latches.
There are several known approaches for reducing switching activity of latches. Clock gating, and in particular sequential clock gating (e.g. observability based), reduces switching activity of latches by preventing clock toggling. However, due to implementation costs of applying clock gating, it can be applied only for sufficiently large groups of latches. Moreover, switching activity reduction is not always guaranteed when using clock gating.
Another approach is FSM encoding
the FSM bits differently such that state transitions incur less switching. However, FSM encoding may add or remove latches.
The idea of the invention is to find groups of correlated latches, i.e. latches which are almost functionally equivalent, and to re-encode the next state functions of those latches such that the entire switching activity of the group is reduced. In each group, one latch is selected and used as the dominator latch for controlling when the other latches of the group load new data, that is may toggle. The decision is based on
whether the controlled latches are about to load value that differs from that of the
dominator. This way the overall switching of the group is reduced since most of the time all the group's latches behave the same.
The advantages of our invention are that it guarantees to not add or remove latches, it and does not have cons...