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Method to automatically find unobservable logic blocks in execution unit designs Disclosure Number: IPCOM000199653D
Publication Date: 2010-Sep-14
Document File: 3 page(s) / 41K

Publishing Venue

The Prior Art Database


Execution units in modern processors usually contain multiple sub-units which carry out various tasks such as arithmetic calculations and logic operations. These sub-units are managed by some control logic which is based on the units op-codes. There may be scenarios in which only a small subset of the sub-units are working while the rest are not being used. A method is described for finding conditions underwhich large logic blocks in execution units, e.g. sub-units, are not being used. The analysis is performed by examining possible op-codes and learning the effect of each of the op-codes on the unit behavior and data flow. The result of the analysis is a mapping from the units op-codes to un-observability conditions of logic blocks as a dependency on number of cycles after the op-code has entered the unit.

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High level design abstraction is beneficial for design automation applications as it allows understanding of data and control flow in a block level granularity. For example, knowing which parts of an execution unit are inactive as a dependency of the current instruction in the pipe may significantly reduce the amount of candidate latches for injection during soft error verification process. One source for this kind of information is design specification documents. These documents describe design intent, such as names of special signals (e.g. pipeline valid) and possible sequences of execution in a pipeline. However, most often those specification documents are not written in such a way that they can be processed by computer programs thus cannot be served as a basis for automatic extraction of high-level behavior of the design. On the other hand, the RTL implementation ,

which can be processed

automatically, embodies designer understanding of the specification, but in low abstraction level. The problem is that the high-level details are obscured by the low-level implementation details. For example, it is hard knowing which are the control signals for a result bus just by looking at the low-level RTL.

A common approach for finding temporarily unused logic cones is based on

the notion of observability. This is usually performed using local analysis of the logic

A major drawback of this approach is that the observability conditions are local,

hence unobservability of large logic blocks is very unlikely to be found, as it may involve sequential analysis. In addition, as those methods do not attempt to separate data signals from control signals, the observability conditions of a given block may become large, making it useless for applications as low power, e.g. using the conditions for clock gating the entire block.

    This invention allows one to use minimal information from the design specification document in order to automatically analyze pipelined execution units and obtain high-level information regarding control and data flow in the unit. Furthermore, the invention allows a program to identify large blocks of logic which are unused (i.e. unobservable) during the unit computation as a dependency of the current instruction in the pipe.
[1] SAT Sweeping with Local Observability Don't-Cares, Qi Zhu, Nathan Kitchen,

Andreas Kuehlmann,

The idea of the invention is to perform 3-value simulation of the execution unit where all the primary inputs of the unit, excluding those related to the unit's instruction bus, are driven by X values. Given a set of legal instructions...