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%MPG% Dynamic Random Access Memory Using Word Line Voltage for NMOS FET Based Array Voltage Regulation Disclosure Number: IPCOM000199687D
Publication Date: 2010-Sep-14
Document File: 2 page(s) / 69K

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The Prior Art Database


Disclosed is dynamic random access memory using word line voltage for NMOS FET based array voltage regulation.

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DRAM array uses regulated voltage supply to guarantee stable operation of bit-line sense amplifier and enough timing margin for cell operation. PMOS FET (M1 in Figure 1) is used as a driving transistor in the regulator. However, a very large width of the transistor is required to drive enough current for parallel bit-line sensing. This large transistor size limits the loop bandwidth of the regulator and requires large standby current of the OP amp. Also, when the external supply (VDD) has AC noise, the internal regulated array voltage (VINTA) also fluctuates because the gate voltage of M1 which is the OP amp output cannot be changed quickly enough due to the relatively low set dominant pole to guarantee the loop stability.

    This invention proposes to use a NMOS FET (M2 in Figure 2) as the driving transistor. For this purpose, higher gate voltage than VDD is required, so the word line voltage (VPP) is use for the OP amp's power supply. This NMOS FET can reduce the driving transistor size so that the regulator's overall response time and OP amp power could be optimized. Moreover, this driving transistor operates as a source follower compared to common source amplifier in conventional case; therefore, it is immune to the external supply (VDD) noise. Figure 3 shows the case where VPP is supplied from the external of the DRAM chip, where this scheme may have more benefit due to more stable VPP po...