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Fabrication method of Au Schottky diode

IP.com Disclosure Number: IPCOM000199830D
Publication Date: 2010-Sep-17
Document File: 4 page(s) / 198K

Publishing Venue

The IP.com Prior Art Database

Related People

Okai Kazuo: AUTHOR [+2]

Abstract

C-V method by Au-Schottky diode is widely used for resistivity measurement especially in n-type Silicon wafer. Generally diode patterning is done by Au evaporation with metal mask on silicon wafer. However, the method causes significant deviation in gate area due to substantial thickness of metal mask (~100 µm), which results in huge error of resistivity. Patterning Au electrode by photolithography is also well known in semiconductor device fabrication. But it requires dry etcher for patterning. The new method described in this document utilizes oxide layer for masking of Au evaporation. The oxide layer is patterned by photolithography technique prior to Au evaporation. The invention utilizes a feature that Au film on oxide layer can be easily removed by adhesive sheet or other mechanical methods. This technique causes very low error in diode area whereby correct resistivity can be measured.

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Fabrication method of Au Schottky diode

C-V測定に用いるAuショットキーダイオードの作成方法

Okai Kazuo(岡井和男), Hiroyuki Deai(出合博之)

   Siltronic Japan Corporation シルトロニック・ジャパン株式会社

Summary

C-V method by Au-Schottky diode is widely used for resistivity measurement especially in n-type Silicon wafer. Generally diode patterning is done by Au evaporation with metal mask on silicon wafer. However, the method causes significant deviation in gate area due to substantial thickness of metal mask (~100 µm), which results in huge error of resistivity. Patterning Au electrode by photolithography is also well known in semiconductor device fabrication. But it requires dry etcher for patterning.

The new method described in this document utilizes oxide layer for masking of Au evaporation. The oxide layer is patterned by photolithography technique prior to Au evaporation. The invention utilizes a feature that Au film on oxide layer can be easily removed by adhesive sheet or other mechanical methods. This technique causes very low error in diode area whereby correct resistivity can be measured.

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1. 背景技術

背景技術背景技術

  従来 Au 電極を Si ウェーハ上に作成する場合、下図の Metal mask に記載されるような方法が利用されてい た。

  しかし、メタルマスクは扱い易さの観点から数百μm の厚みを持っているため、下図のように影に相当す る部分が無視できない。このため、出来上がったショットキーダイオードは面内にばらつきを持ってしまう。 また開口部の面積が遮蔽部に比べて大きくなると、メタルマスクが変形しやすくなり、ウェーハに密着しづ らくなってしまうため、面内に作成...