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Browse Prior Art Database

Meta-Core Processors

IP.com Disclosure Number: IPCOM000199834D
Publication Date: 2010-Sep-17
Document File: 6 page(s) / 138K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document describes a proposal to leverage the Moore’s Law based, exponentially increasing thread and core counts of a multi-core and the physical proximity of neighboring threads and cores to enable meta processing via meta threads. Unlike the program-level assist processing implemented by traditional helper and slave threads, meta processing is processing that orchestrates and improves the execution of regular processing at a control level, via managing program execution, configuring hardware, and runtime-optimizing regular programs.

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Meta-Core Processors

Introduction

Multi-core processors currently incorporate several (say 2 to 8) simple processor cores in close

physical proximity on a single processor chip, with the core count going up to 64 in a Tilera

Corp. multi-core and 80 in an Intel research multi-core prototype. The core count is expected to grow exponentially, tracking Moore's Law. The cores are physically very close to each other, resulting in inter-core communication for physically neighboring cores incurring the same small clock count as say access to a core's local primary cache. Some multi-cores such as the Tilera

processor already employ point-to-

and layout of the cores on the chip.

Each core of a multi-core is typically simultaneously-multithreaded (SMT). Such an SMT core typically issues instructions from multiple independent threads each clock cycle, one instruction

per thread. Each thread has its own register file in the core, but most of the other control and data

paths of the core are shared by all the threads. The register files of the different threads are in

fact implemented as portions of a common large physical register file. These facts imply that inter-thread communication hardware within a single SMT core can be implemented with the same cycle costs as local register access.

This document describes a proposal to leverage the Moore's Law based, exponentially increasing thread and core counts of a multi-core and the physical proximity of neighboring threads and cores to enable meta processingviameta threads . Unlike the program-level assist

processing implemented by traditional helper and slave threads,

                                     meta processing is processing that orchestrates and improves the execution of regular processing at a control level , via managing program execution, configuring hardware, and runtime-optimizing regular programs. Meta threads run on dedicated SMT threads or whole cores to implement meta processing. We

propose hardware-complexity-effective enhancements to processor cores to provide hardware

assist to meta threads so as to make meta processing efficient.

Meta-Core Enhancements to Regular Processor Cores

We propose enhancements to regular processor cores primarily in the form of exposing existing architectural and micro-architectural control and data paths of a hardware-thread/core to software threads running on neighboring SMT threads/cores. We also propose some additional simple architectural and micro-architectural hardware control structures that enable further efficiency of meta threads; these new structures are also exposed to software threads.

We describe a scenario where the exposed hardware structures are accessed via memory mapping, so that regular LOAD and STORE processor instructions to specially designated memory addresses can access these structures. However, this is without loss of generality: where

practically feasible, the processor's instruction set can be enhanced with special instructions

point on-chip interconnect...