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A pseudo hierarchy approach for improved performance and reduced logic overhead in very high speed processors

IP.com Disclosure Number: IPCOM000199907D
Publication Date: 2010-Sep-21
Document File: 6 page(s) / 146K

Publishing Venue

The IP.com Prior Art Database

Abstract

VLSI circuits in the range of multiple gigahertz (GHz) are critical for timing and require timing and parasitic extraction at the device level. Given the complexity of a microprocessor in terms of gate count and performance, the logic has to be partitioned into several smaller macros which make it easier for the tools to implement the logic. The complete design cannot be extracted and timed at the flat hierarchy because of the huge memory requirement and run time cost. This makes the flat approach impossible to adopt. However, the flat approach has its advantages in optimization and power. A flat hierarchy allows better optimization across the boundaries, optimizes area and power and avoids need for complicated boundary contracts and budgeting. Outlined below is a method that can be used in-order to have the advantages of a flat approach and at the same time to be able to extract at a device level without a major hit in the runtime and memory.

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A pseudo hierarchy approach for improved performance and reduced logic overhead in very high speed processors

This invention is related to digital IC design using EDA tools particularly to physical design of microprocessors like chips using standard cell components.

The traditional design flow of designing a digital integrated circuit (IC) is using the following flow

Establishing architectural and electrical specifications


High level design
Low Level Design with the help of RTL (Register Transfer Level) coding using a Hardware description language ( HDL )

RTL simulation to verify the functionality of the design
Synthesis of the RTL code to produce a technology dependent netlist
Formal verification is done to verify functionality is maintained between RTL and layout
Pre-layout chip level static timing verification;

Floorplanning and Placement
Clock tree synthesis
Wiring
Post layout timing sign off STA
IR drop and noise signoff
Physical Verification - Design rule check and Layout Vs Schematic

The concept or the specification is first established as an architecture and electrical specification. This is called High level design. This is then broken down into detailed level design or also called as low level design using a hardware description language ( HDL ) like Verilog or VHDL. This is technology independent.

The design is now translated into a technology dependent netlist using a method called gate level synthesis. The inputs to synthesis in design constraints in the form of timing, area and power for the design.

The output of synthesis is called a netlist and has the design abstracted in the form of gates, which is technology dependent.

After this is done, the design goes through physical optimization which is placement aware and synthesis transforms are done using the placement information.

Clock trees are generated based on the placement of the latches in the design.

The last step is to route or wire the design using a router which obeys the design rules from the foundry. The design rules are inputs to the router and are described later in this document in greater detail.

The final step is physical verification - which is DRC and LVS.

DRC ( Design Rule Check ) checks adherence of the design to the foundry design rules. This contains rules which make the design manufacture able /

For e.g., spacing rules, width rules for the wires, density rules, antenna rules. Violation of these rules could result in a non working chip or a very low yield . Hence DRC is absolutely necessary to pass for the chip to function.

LVS is Layout Vs Schematic and checks if there is a proper match between layout and schematic of the design. Any shorts or opens in the layout would be checked in this step. Failure in LVS will result in a non working chip.

In a microprocessor design, the complexity of the logic in terms of gate count is very high. The performance and power requirements are very high as well.

Typically, the microprocessor is divided into several units...