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Voltage translation scheme with improved performance

IP.com Disclosure Number: IPCOM000199909D
Publication Date: 2010-Sep-21

Publishing Venue

The IP.com Prior Art Database

Abstract

Present invention describes a novel voltage translation scheme which permits wide range of voltage translation with improved performance and less power consumptions

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 45% of the total text.

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Voltage translation scheme with improved performance

For complex SoC design in UDSM technology nodes, 45nm and below, multiple power domain is a need to achieve optimum performance power ratio. Wide range & low power voltage translators are required to translate one voltage level to other voltage to enable the optimum performance ratio in such complex SoC's.

Different type voltage translation circuits has been proposed so far. Existing solutions are unable to address the requirement of wide range voltage translation with improved performance and reduced power.

One possible solution to existing problem is an invention titled "Single supply level converter" Patent number - US 7,336,100 B2, attached doc. "prior

_

          1.pdf" . This solution involves dynamically switching the supply of first inverter in the circuit (sown in Fig. 1, under summary of invention) between "VDDH-2Vtn and VDDH.

When input "IN" is high, the supply voltage "VS" of first inverter approaches to VDDH-2Vtn" , reducing the gate to source voltage of PMOS MP2 to turn it OFF quickly.

When input "IN" is low, the feedback transistor MP1 turns ON and charges the node "VS" to VDDH to compensate the drop at node " VS". In this scheme, High to Low transition has performance penalty due to voltage drop at node "VS" below "VDDH-2Vtn" (as shown in Fig. 8, under summary of invention).

The node "VS" drops below "VDDH-2vtn" because of charge sharing among "VS" and IN

_B, as MP2 is ON. The node

                               "VS" will start pre charging to VDDH only when OUT node goes "0" and MP1 is turned ON.

This also has impact on power because, node "VS" needs to be pre charged to VDDH from a lower voltage level ( below VDDH-2Vtn). Simulation result clearly indicate the performance & power degradation as in Table 1, under summary of invention.

Another possible solution to existing problem is paper titled "A new level shifter with low power in multi voltage systems", by "Bo Zhang, Liping Liang, Xingjun and Wang, attached doc. "prior

_art

_art

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2.pdf".

1

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Implementation of this scheme is shown in Fig. 2, under summary of invention.

    This scheme also has performance degradation as discussed in case of prior

_art

_1 above, this is shown in Fig. 9, under summary of invention.

Another drawback of this scheme is shown in Fig. 10, under summary of invention. When VDDL=0.45V, this scheme doesn't work.

Present invention describes a novel voltage translation scheme with improved performance and less power.

It permits :

    - Wide range voltage translation with improved performance and less power

The component of invention includes:

    - Voltage translation circuit along with reference voltage generation

    - Reference voltage generator circuit for controlled voltage generation

Advantages of the invention:

- Wide range operation

- Improved performance

- Reduced power

Fig 3. shows the implementation of proposed voltage translation scheme. This circuit comprises level shifter block along with reference voltage generation c...