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Methodology for instruction consistency validation using register facility

IP.com Disclosure Number: IPCOM000199918D
Publication Date: 2010-Sep-21
Document File: 4 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Consistency validation of processor is one of the major challenges in the chip design area. General methods of consistency validation include running the stream multiple times and expecting the same output after every run. Here memory is extensively used for storing and retrieving results for validating the consistency of the instruction set. It also includes memory operations for reloading and initializing the test case for the consecutive runs. Due to extensive memory usage for results comparison and test case initialization, lot of processor cycles is wasted on the way. The technique proposed here is an alternative test methodology for validating the instruction set architecture of the microprocessor. The approach presented here tries to avoid the memory related operations completely for result comparison and test case initialization for consecutive runs and to some extend it even avoids the re-building of test cases.

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Methodology for instruction consistency validation using register facility

Consistency validation of processor is one of the major challenges in the chip design area. General methods of consistency validation include running the stream multiple times and expecting the same output after every run. Here memory is extensively used for storing and retrieving results for validating the consistency of the instruction set. It also includes memory operations for reloading and initializing the test case for the consecutive runs. Due to extensive memory usage for results comparison and test case initialization, lot of processor cycles is wasted on the way. The technique proposed here is an alternative test methodology for validating the instruction set architecture of the microprocessor. The approach

presented here tries to avoid the memory related operations completely for result comparison and test case

initialization for consecutive runs and to some extend it even avoids the re-building of test cases.

The idea behind the proposal is to bring out a consistency validation methodology using readily available general purpose registers, i.e. technique is to use the register facility as a medium for the consistency validation. Today's RISC architectures are sculptured with large register files. Proposed technique is to split the available general purpose register file into two halves and to select a set of the pseudo random instructions which will operate on both the register halves and finally the registers are compared at the end of the test run for the correctness of the hardware. 64 bit PowerPC® architecture is taken as the reference platform to explain our idea.

A test case T will have two halves T(a) and T(b), though the base instruction opcode in both the halves are identical, the registers used by these instructions are different. Since both set of registers are initialized with same identical data, final result comparison is made simple. Correctness of the hardware is validated by comparing the registers halves 'a' and 'b'.

Validation using memory based facility waste a lot of cycle counts in fetching and storing the computed results from and in a relatively very slow main memory. This huge cycle wastage is capitalized by the register facility based validation method. This method achieves it's through put by reducing the cycle counts wasted in memory based result comparison and context switch.

It reduces the cycle count in building another test case by re-running the same test case with different set of input data which resulted as an output from the previous run. Even though the method validates the instructions by executing twice with same given input, it does it in a same pass avoiding a context switch in between them, i.e. since the test case in this method has two parts T(a) and T(b), the same instruction will occur in both of the halves giving a look and feel of two pass stream validation.

Test case Generation:

Test case buildi...