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A Novel Test Pattern to Detect Unstable Failing Bits Sensitive to Neighborhood Patterns in a Wide-Word Embedded DRAM

IP.com Disclosure Number: IPCOM000199949D
Publication Date: 2010-Sep-21
Document File: 6 page(s) / 31K

Publishing Venue

The IP.com Prior Art Database

Abstract

A novel test pattern was invented to detect unstable failing bits sensitive to neighborhood patterns (UNPSF) in a wide-word embedded DRAM. In embedded application, while testing the memory in a BIST mode, one does not have the luxury of indefinitely varying the bit patterns around a failing bit. This is because bit-level write and read control of embedded memory often do not exist in BIST mode. A pseudo-random bit pattern based approach is proposed to overcome this limitation to detect UNPSF’s and cost savings calculated.

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A Novel Test Pattern to Detect Unstable Failing Bits Sensitive to Neighborhood Patterns in a Wide-Word Embedded DRAM

Indrajit Manna, James Pfiester and Jason Brown Avago Technologies, Fort Collins, CO 80525

Abstract

A novel test pattern was invented to detect unstable failing bits sensitive to neighborhood patterns (UNPSF) in a wide-word embedded DRAM. In embedded application, while testing the memory in a BIST mode, one does not have the luxury of indefinitely varying the bit patterns around a failing bit. This is because bit-level write and read control of embedded memory often do not exist in BIST mode. A pseudo-random bit pattern based approach is proposed to overcome this limitation to detect UNPSF's and cost savings calculated.

Introduction and Background:

An extensive number of test patterns are used for detecting faults in an embedded DRAM application. Most commonly used test patterns in embedded memory applications are designed to look at stuck-at-faults, transition faults and coupling faults. The patterns used for detecting these faults vary from simple scan (0/1) tests, checkerboard tests and various forms of March tests (such as MarchX, March C-, MATS etc.). With proper data background initialization, the above patterns are usually quite sufficient to detect most of the time-invariant (i.e. "stable") faults found in the embedded DRAMs.

However, there are certain types of faults that are only sensitized by specific patterns in the neighborhood of a bitcell. These are called neighborhood pattern sensitive faults. The only way to sensitize these faults is to transition the bits that are physically located nearby (so-called "deleted neighborhood" [1]) to zeros and ones independently of each other. For each bit cell with 4 nearest neighbors (two on the same bit line and two on the same word lines, see Fig.1), this means as many as 32 patterns (i.e four neighborhood cells are transitioned from 4'b0000 to 4'b1111 with the base cell remaining either at 1'b0 and 1'b1, see Fig. 2). If one includes so-called the type-II neighborhood (i.e nearest 8 or 15 cells surrounding the base cell), the number of patterns increase exponentially.

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d1

Base

Cell d4

d2

Fig.1: The immediate neighborhood of a base cell. d1 and d2 share the same column with the base cell and d3 and d4 share the same row with the base cell.

Fig. 2: An example of 32 test patterns (single BIST run) to detect neighborhood sensitive fault for a single base cell. The number of patterns increases exponentially if a larger neighborhood is tested.

Also in order to apply such patterns for neighborhood sensitization, the BIST has to be able to control each bit of the memory at the bit-level. In modern embedded DRAMs with wide words and complex scrambling table, the complexity required for the BIST to implement such patterns becomes very high.

Add to this sometimes unstable nature of such fault and multiple BIST runs are required to capture the location of the fault....