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Solving Testcube Issue by Splitting Capture Procedure to Get Test Coverage

IP.com Disclosure Number: IPCOM000199977D
Publication Date: 2010-Sep-22
Document File: 5 page(s) / 434K

Publishing Venue

The IP.com Prior Art Database

Abstract

Scan and ATPG tools like TestKompress (by Mentor Graphics) use EDT technology to achieve compression of scan test data by controlling a large number of internal scan chains using a small number of scan channels. In this process, the tool creates a test cube filled with a few care bits and lots of pseudo-randomly-generated don't care bits to test a particular fault site. The creation of test cube is actually a combination of a large number of simultaneous equations in which too many care bits can make it impossible for the tool to solve the system of equations. Failure to simultaneously create all the care bits required to test a particular fault site results in test cube issue.

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Solving Testcube Issue by Splitting Capture Procedure to Get Test Coverage

Abstract

Scan and ATPG tools like TestKompress (by Mentor Graphics) use EDT technology to achieve compression of scan test data by controlling a large number of internal scan chains using a small number of scan channels. In this process, the tool creates a test cube filled with a few care bits and lots of pseudo-randomly-generated don’t care bits to test a particular fault site. The creation of test cube is actually a combination of a large number of simultaneous equations in which too many care bits can make it impossible for the tool to solve the system of equations. Failure to simultaneously create all the care bits required to test a particular fault site results in test cube issue.

In case of transition pattern generation where clock and scan enable are controlled through a series of register banks, a large number of flops need to be constrained during capture cycle. This idea provides the solution to be used when these numbers of constraint exceeds ATPG tool handling capability and ATPG tool is not able to generate any pattern.

This idea involves reduction of number of constraints such that if the ATPG tool is not able to satisfy all the care bits, it will split the number of care bits into multiple sets enabling different sets in different capture procedures to generate patterns. Considering the scenario when clocks/scan enables to different modules (blocks) are controlled by different register banks and driven from the same compression engine, only few modules are enabled in any capture procedure and clocks to other modules are forced to 1’bX and vice versa in the remaining capture procedures. The advantage of using this approach is that at least the transition coverage within the modules can be recovered. The only coverage loss is the coverage of paths between the blocks. With this approach most of the ATPG coverage can be recovered. If care is taken in selecting the modules to be enabled in a particular capture procedure, coverage loss can be minimized.

Detailed Description of the idea

Consider the case of figure1 in which block1 and block2 use the same compression engine while they have their own register banks (16 flops each ) to control the clock enable (CE register bank) and scan enable (SE register bank). In the normal case when ATPG tool tries to generate transition patterns for this design, it needs to control all the 32 flops in a single capture procedure.

In this case it will be able to cover faults within the block1 and block2 and faults in the path of interaction between block1 and block2.But the number of constraints (32 flops) may exceed the ATPG tool capability to handle and place care bits on a...