Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Amplifier bias circuit for extended linear range and improved efficiency

IP.com Disclosure Number: IPCOM000200011D
Publication Date: 2010-Sep-23
Document File: 2 page(s) / 312K

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper describes a bias circuit which solves the degradation of linearity of an RF amplifier when the input signal level is increased. The solution adds a capacitor to a buffered current mirror bias circuit which stabilizes the RF bias current flowing through the current mirror. In addition to improving linearity, the efficiency of the amplifier is also improved.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 50% of the total text.

Page 01 of 2

Amplifier bias circuit for extended linear range and improved efficiency

Yut Hoong Chow, Wai Cheng Chan Avago Technologies (M) Sdn Bhd

currents such as in deep Class-AB compared to close to Class-A bias.

   Fig 2 shows the CW plot of gain vs output power (Pout) of the amplifier at two different deep Class-AB conditions.

(This page contains 00 pictures or other non-text object)

(This page contains 01 pictures or other non-text object)

   Fig 2 - Gain vs Pout at two different bias conditions for a deep Class-AB biased amplifier

Fig 3 below shows the linearity as measured by the output third-order intercept point (OIP3) vs input power (Pin). There is significant reduction of the OIP3 as Pin is increased.

(This page contains 02 pictures or other non-text object)

(This page contains 03 pictures or other non-text object)

(This page contains 04 pictures or other non-text object)

(This page contains 05 pictures or other non-text object)

(This page contains 06 pictures or other non-text object)

(This page contains 07 pictures or other non-text object)

(This page contains 08 pictures or other non-text object)

(This page contains 09 pictures or other non-text object)

(This page contains 10 pictures or other non-text object)

(This page contains 11 pictures or other non-text object)

(This page contains 12 pictures or other non-text object)

(This page contains 13 pictures or other non-text object)

(This page contains 14 pictures or other non-text object)

(This page contains 15 pictures or other non-text object)

(This page contains 16 pictures or other non-text object)

Fig 3 - OIP3 vs Pin for amplifier above

Improved bias circuit with enhanced linearity and efficiency

An improvement to the linearity performance can be achieved if the bias current through Q2 is maintained as constant as possible as the input signal is increased. This is important because of the finite isolation between the signal at the input to the gate of Q1 and the bias circuit.

Fig 4 below shows the improved bias circuit with the addition of capacitor Cb and the splitting up

Abstract

This paper describes a bias circuit which solves the degradation of linearity of an RF amplifier when the input signal level is increased. The solution adds a capacitor to a buffered current- mirror bias circuit which stabilizes the RF bias current flowing through the current mirror. In addition to improving linearity, the efficiency of the amplifier is also improved.

Variation of linearity of a RF amplifier with input signal change

A typical RF amplifier with bias circuit is shown in Fig 1 below. The amplifying FET Q1 is biased by a buffered current mirror comprising Q2 and Q3. R1 and Q2 establish a reference current for Q1.

Fig 1 - RF amplifier circuit with bias circuit

Under small-signal conditions, Q3 buffers the bias voltage VgQ2 so that any variations due to temperature or voltage across R1 is reduced. However, there is a limit to how much Q3 can stabilize VgQ2 due to voltage variations across R1. When the inp...