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Browse Prior Art Database

A RAID Controller With A Tiered Cache Bank

IP.com Disclosure Number: IPCOM000200122D
Publication Date: 2010-Sep-29
Document File: 1 page(s) / 18K

Publishing Venue

The IP.com Prior Art Database

Abstract

A RAID controller is disclosed with a tiered cache bank. The tiered cache bank includes a DRAM based cache and one or more flash based caches.

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This is the abbreviated version, containing approximately 80% of the total text.

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A RAID Controller With A Tiered Cache Bank

Disclosed is a RAID controller with a tiered cache bank. The tiered cache bank includes a DRAM based cache and one or more flash based caches.

The DRAM based cache is stored in a top-tier of the tiered cache bank. The RAID controller uses the DRAM based cache primarily to store writes. The DRAM based cache uses standard LRU or MRU algorithms for eviction of data from the DRAM based cache.

The one or more flash based caches are stored in a next tier of the tiered cache bank. In an embodiment, the one or more flash based caches may be populated with data which is evicted from the DRAM based cache. In another embodiment, a code may be written to keep counters on granularity of a RAID strip. Segments which are accessed the most are copied into the one or more flash based caches. Further, predictive population into the one or more flash based caches can be done by dividing counters up into times of day or weeks/months. A cache can elect to populate cache (and evict to make room for based on predicted lower access) based on past usage for that time period.

Since the number of counters may be high, the counters themselves can be cached into DRAM based cache. The counters would permanently reside in the one or more flash based caches but those most recently accessed would reside in the DRAM based cache.

In an embodiment, the tiered cache bank's power source is supplemented with an energy storage device such as, but not limited...