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Large-Scale Graphene Transistors with Enhanced Performance and Reliability Based on Interface Engineering by Phenylsilane Self-Assembled Monolayers

IP.com Disclosure Number: IPCOM000200125D
Publication Date: 2010-Sep-29
Document File: 4 page(s) / 45K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an invention for bottom-gated, large-scale chemical vapor deposited (CVD) graphene transistors designed by applying molecular phenyl-terminated organosilane self-assembled monolayers (SAM) onto the dielectric surface. The result is more reliable, more stable, and faster large-scale graphene transistors.

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Large-Scale Graphene Transistors with Enhanced Performance and Reliability Based on Interface Engineering by Phenylsilane Self -Assembled Monolayers

Graphene, an atomically thin layer of 2-D carbon film, has emerged as a promising candidate material for high-speed nanoelectronics due to its extraordinary electrical and optical properties. Among many other applications, the graphene field-effect transistor (FET) is recognized to be a possible alternative to traditional silicon FET for the next generation of very large scale integration (VLSI) circuits, particularly radio-frequency (RF) electronics. The intrinsic mobility of graphene has been predicted to reach 200,000 cm2/Vs at room temperature. However, the field-effect mobility of graphene transistors as fabricated on dielectric substrates (e.g. SiO2 ), is typically multiple orders of magnitude lower, along with unfavorable bias stress instability and hysteresis behavior in the electrical characteristics.

A primary source that limits the graphene FET performance and reliability lies with the dielectric/graphene interface, where a variety of scattering and trapping effects present. In addition to the intrinsic graphene acoustic phonon scattering, Coulomb impurity, surface roughness, and surface polar phonon scatterings from the adjacent dielectric can all affect charge transport. These scatterings may become especially pronounced for device operation at room temperature. This is corroborated by the fact that suspended graphene does not suffer from extrinsic scatterings, and thus is ideal for studying intrinsic graphene properties. For device applications, finding proper non-polar substrates might be helpful and necessitated, yet it remains a challenge.

Recent work using a hydrophobic hexamethyldisilazane layer as the silicon oxide surface modifier or using a single crystal hexagonal boron nitride (h-BN) as the substrate shows promising results; whereas, thus far, they are for exfoliated graphene flake transistors, which are hardly scalable for technological applications. Also, the interface physics for the graphene transistor performance and reliability still requires further exploration.

The disclosed invention reports bottom-gated, large-scale chemical vapor deposited (CVD) graphene transistors by applying molecular phenyl-terminated organosilane self-assembled monolayers (SAM) onto the dielectric surface. CVD graphene is employed here due to its large scalability and manufacturability for device integration. The invention illustrates that the phenyl-alkyl-SAM-based interface engineering consistently improves the CVD graphene FET mobility, hysteresis and bias stress stability; thus, it is promising for practical applications. Through a systematic measurement and model fitting for graphene transistors with and without the phenyl-SAM, the invention clarifies the physical mechanisms responsible for the observed FET mobility, hysteresis, and bias stress behavior.

The invention was...