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Alignment Marks for Edge of Memory Cube

IP.com Disclosure Number: IPCOM000200129D
Publication Date: 2010-Sep-29
Document File: 1 page(s) / 18K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for setting vertical alignment marks in the dicing channel on the edge of a memory cube to allow accurate alignment of the edge metal layer to the last metal layer.

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Alignment Marks for Edge of Memory Cube

3D integration can provide performance advantages for microprocessors by allowing for larger cache memory, shorter interconnects, and higher bandwidth (1). One 3D approach attaches memory strips onto a microprocessor (4DI process).

A challenge with the 4DI process is that processing is required on the edges of the memory strips, including fabrication of wiring. Wire fabrication on the edge of the memory strips requires alignment of the edge wire pattern to the last metal wiring at the edge of the memory strips. Hence, alignment marks are required on the edges of the memory strips. In previous memory cube technology (not published), alignment marks were formed using last metal wiring. However, this limits alignment and overlay to one direction (e.g., "x" direction), which in turn, restricts the minimum wiring pitch of the edge wires. It is desirable to have a set of alignment marks on the edge of the memory strip that allow alignment and overlay measurements in two orthogonal directions (e.g., "x" and "y"). This allows for a smaller wiring pitch along the edge of the memory strip
(y).

The invention allows accurate alignment of the edge metal layer to the last metal layer (on memory strips) by adding vertical align marks in the dicing channel (i.e., such that the vertical marks are visible after dicing). The vertical alignment marks can be formed using stacked metal "bars" and/or by using trenches in the Si (STI, shallow tre...