Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method of Reducing Tests Involving State-Dependent Timing

IP.com Disclosure Number: IPCOM000200130D
Publication Date: 2010-Sep-29
Document File: 3 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for reducing the number of clock gating tests in state-dependent timing based on the propagation of the delays.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 3

Method of Reducing Tests Involving State -Dependent Timing

The problem that this invention addresses involves complex logic circuits that have

modeled state-dependent timing arcs in their timing rule. When logic constants are

present at input states which match a certain 'when' condition, the static timer analyzes

only the timing arc for the logically active state. When logic constants are not present,

the timer must analyze all arcs with different combinations of the 'when' conditions and

propagates timing for all conditions. When a gate is in a clock gating situation that

contains 'when' conditions, the timer performs clock gating tests for all combinations of

the 'when' conditions. Evaluating all combinations of clock gating tests results in

relatively larger runtimes. After the analyzer propagates timing, only one of the timing

arcs from the pin is propagated.

The following is an example of the number of clock gating tests run based on the

propagation of the delays:
If A1 (clock) and B1 (data) pins are in a clock gating scenario, then the static timing

engine performs tests between A1 and B1 for all possible combinations of

propagation from A1 and B1 to Y:
A1->Y when !B0&!B1, B1->Y when !A0&!A1

1.

A1->Y when !B0&B1, B1->Y when !A0&!A1

2.

A1->Y when B0&!B1, B1->Y when !A0&!A1

3.

A1->Y when !B0&!B1, B1->Y when !A0&A1

4.

A1->Y when !B0&B1, B1->Y when !A0&A1

5.

A1->Y when B0&!B1, B1->Y when !A0&A1

6.

A1->Y when !B0&!B1, B1->Y when A0&!A1

7.

A1->Y when !B0&B1, B1->Y when A0&!A1

8.

A1->Y when B0&!B1, B1->Y when A0&!A1

9.

Fewer tests for timing analysis to process would result in a reduction of runtime for

subsequent analysis.

The solution presented here is to reduce the number of clock gating tests based on the

propagation of the delays. Since the timer only sees the arrival time at the Y pin due to

one segment from A1 and one segment from B1, the timer should also perform the

clock gating test using only those two segments.

1


Page 02 of 3

The following is an example of how the system works where the clock gating setup test

has a data signal reaching B1 pin and a clock signal reaching A1 pin:
• The system tests the late data signal from B1 against the early clock signal from

A1.
• The Y pin sees the latest of the late arrival times from...