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Method and System for Testing and Diagnosing Through-Silicon Via (TSV) in Three-Dimensional (3D) Integrated Circuits (ICs)

IP.com Disclosure Number: IPCOM000200333D
Publication Date: 2010-Oct-06
Document File: 5 page(s) / 160K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for testing and diagnosing Through-Silicon Via (TSV) in Three-Dimensional (3D) Integrated Circuits (ICs) is disclosed. The method involves differentially determining Alternating Current (AC) conductivity defects in TSVs based on Design For Test (DFT).

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Method and System for Testing and Diagnosing Through -Silicon Via (TSV) in Three-Dimensional (3D) Integrated Circuits (ICs)

Disclosed is a method and system for testing and diagnosing Through-Silicon Via (TSV) in Three-Dimensional (3D) Integrated Circuits (ICs). The method involves differentially testing TSVs based on Design For Test (DFT). Initially, a shmoo test is applied on a first layer of the 3D IC. The shmoo test is applied by launching test data by latches on a first layer of the 3D IC which are scan enabled. In a scenario, result of the test data is captured by TSV latches on the first layer of the 3D IC. In another scenario, the result of the test data is captured by TSV latches on second layer of the 3D IC. The test data may have a deterministic pattern from an external tester. Alternatively, the test data may have a Logic Built-In Test (LBIST) pattern internally generated using a Pseudo Random Pattern Generation (PRPG). Further, the test data may be used for creating specific diagnostic test pattern for determining Alternating Current (AC) conductivity defects in the TSVs. In addition, a time difference between the TSV latches is measured. The time difference between the TSV latches represents a TSV delay.

The method and system for determining AC conductivity defects in the TSVs is illustrated in Fig.1.

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Figure 1

As shown in Fig. 1, the AC conductivity defects in the TSVs are determined using a DFT structure. Initially, a shmoo test is performed on a TSV such that a launch latch and a

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capture latch are on the same layer of the 3D IC as shown in Fig. 2.

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Figure 2

As shown in Fig. 2, a scan chain 1 launches a test data. In a scenario, the result of launching the test data is captured by a scan chain 2. In another scenario, the result of the test...