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A Method and System for Scan Chain Optimization Across Multiple Chains

IP.com Disclosure Number: IPCOM000200365D
Publication Date: 2010-Oct-08
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Digital integrated circuits typically contain scan chains which allow for fast loading and unloading data into storage elements. The scan connections may use a significant amount of the available wiring tracks and thereby create wiring congestion. A system is presented that allows for swapping storage elements within one scan chain and across multiple scan chains.

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A Method and System for Scan Chain Optimization Across Multiple Chains

1. Previous work

Scan chains are defined in logic design. Physical design may reorder elements within scan chains in order to reduce the amount of wiring tracks being used.

The picture below shows a multiplexed scan connection.

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2. New Approach

Scan related objects must fulfil certain requirements in order to allow for testability. Potential requirements are:

1. A storage element must belong to a certain group of scan chains or one particular chain.

Example: The scan chain is being used for resetting storage elements.

2. A storage element must be in a certain position range or at a particular position in a scan chain.

Example: An SRAM must always be at the end of a scan chain.

3. The number of bits in a scan chain must be in a certain range. Note that storage elements may have more than one bit and more than one scan inputs and outputs.

We assume that the netlist complies with all the requirements above. We propose the method outlined below. The picture illustrates an example containing six registers (one bit storage elements) in two scan chains. We assume that all registers belong to the same equivalency group.

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1. Add dummy registers to each primary input and primary output. These registers are being placed close to the corresponding primary inputs and outputs in the layout.

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