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Dynamically Configurable Low Power System

IP.com Disclosure Number: IPCOM000200582D
Publication Date: 2010-Oct-19
Document File: 5 page(s) / 92K

Publishing Venue

The IP.com Prior Art Database

Abstract

Low end and Ultra low end markets are severely cost sensitive. SoCs today are designed to cater to multiple market segments. This leads to over budgeting on Peripheral interfaces e.g. multiple PCIe, Ethernet, USB etc. and Processing power (e.g. additional CPU cores). The available Peripheral interfaces and Processing power may not be needed for all applications scenarios and it impacts power and overall Cost of the device. The proposed approach presents a mechanism to reduce both the default and runtime power of the SoC. Lower default power also helps in selecting lower cost package for market segments where the default configuration suffices.

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Dynamically Configurable Low Power System

Abstract

Low end and Ultra low end markets are severely cost sensitive. SoCs today are designed to cater to multiple market segments. This leads to over budgeting on Peripheral interfaces e.g. multiple PCIe, Ethernet, USB etc. and Processing power (e.g. additional CPU cores). The available Peripheral interfaces and Processing power may not be needed for all applications scenarios and it impacts power and overall Cost of the device. The proposed approach presents a mechanism to reduce both the default and runtime power of the SoC. Lower default power also helps in selecting lower cost package for market segments where the default configuration suffices.

Body

Problem description

Figure 1. Conventional SoCPower up State

       SoCs with or without power partitions are powered up at full configuration after reset, as shown in the Figure 1 above. This leads to:

v  Increased power & cost:

¨       The device boots with full configuration after reset. Even at run time, the unused Peripheral Interfaces are kept

Power

ON

. This necessitates SoC package to withstand higher thermal limits.

¨       All Peripheral Interfaces are bond out on package leading to increased number of package balls

¨       The package cost is driven by its thermal limits and balls.

v  Increased BOM cost for customers: PCB design has to support full blown power supply, high rated voltage regulators, heat sync, air flow etc.

       Sub optimal use of processing power.

v  All applications do not need full processing power available and/or all the peripheral interfaces like multi USB/Ethernet/PCIe etc.

v  This further adds to device run time power

The Solution

The method proposes an approach to reduce both the default power (after reset) as well as run time power. This gives flexibility to the customers in designing their boards as per their application requirement. Customers can be benefited from the reduced solution/s...