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Method of Post-Silicon Optimization of SRAM Utilizing BTI during Burn-In

IP.com Disclosure Number: IPCOM000200646D
Publication Date: 2010-Oct-22
Document File: 3 page(s) / 139K

Publishing Venue

The IP.com Prior Art Database

Abstract

Increased process variation and device mismatch in nm technologies adversely affects the stability of conventional 6-T SRAM cell. Under ideal manufacturing conditions, the two back-to-back inverters that constitute an SRAM cell will be identical and exactly matched. However, with process variation, one (or more) of the SRAM cell devices are stronger (or weaker) than the rest, creating an inherent imbalance in the cell. This results in reduced cell stability and consequently in SRAM yield. In this document, a methodology to enhance yield by utilizing bias temperature instability via pre-conditioning of the SRAM cell states during burn-in is presented.

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Method of Post-Silicon Optimization of SRAM Utilizing BTI during Burn -In

Motivation

The stability of the conventional 6-transistor (6-T) SRAM (shown in Fig. 1) is dependent on the relative strengths of the various transistors in the cell. The transistors on the left and right side of the cell are sized identical so that the resulting cell is symmetric in its characteristics. However, due to process variations, certain devices become stronger than their counterparts, and hence the cell becomes asymmetrical. The stability of the cell is determined by its weakest side, and hence the cell stability degrades.

In most current designs, a burn-in process is used to detect early failures in the life of the manufactured product (design). In a typical burn-in process, the devices are subjected to a higher temperature and voltage condition, with the objective being to create a high electric field across the design. This helps identify weak spots in the design, which fail under these high stress conditions.

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Fig. 1 A 6-T SRAM Cell. To achieve a symmetric cell, PL is identical to PR, NL is identical to NR, AL is identical to AR.

However, under these stress conditions, all devices undergo some degradation due to a

  henomenon called bias temperature instability (BTI). The devices undergo a threshold voltage shift (towards higher values) under constant gate bias. The extent of shift increases under stress conditions, as shown in Fig. 2. Hence, the condition (value) of the SRAM cells under these stress condition becomes important. Typically, the cells are maintained at logic '0' for half the duration of burn-in and at logic '1' for the remainder of the duration in an attempt to maintain symmetry in the cell. However, if the cell is asymmetric at the beginning, it will continue to be asymmetric after burn-in. This document proposes pre-conditioning the SRAM cells prior to burn in to a value that helps improve the symmetry in the cell.

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Fig. 2 Degradation of device threshold voltage under different voltage stress.

Key Idea

The main idea in this approach is to identify the weak side of the cell, and to bias the cell prior to burn in such that the weak side does not experience BTI-caused degradation. The wea...