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Dual-Speed Level Shifter with Analog Mode Control

IP.com Disclosure Number: IPCOM000200724D
Publication Date: 2010-Oct-26
Document File: 5 page(s) / 753K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a dual-speed level shifter with analog mode control.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 19% of the total text.

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Level translator circuits are commonly used to pass signals across voltage domain boundaries. Many different level translators exist, but most suffer from frequency range limitations. Some topologies function well at low frequencies, but cannot pass signals in the GHz range [1]. Others
[2] work well when tuned to run in the GHz range but suffer from voltage overshoots and duty cycle issues at low frequencies. This invention extends the frequency range of a single level-shifting system by combining both an ac-coupled and traditional low-speed level-shift circuit and automatically shifting between them when voltage overshoot conditions are detected.

    One application where this circuit would be useful is in a PLL (see Figure 1). Many PLL's have one voltage domain for all the analog circuits (PFD, CP, VCO), and another voltage domain for the digital circuits (dividers, control logic, etc.). As a result, a level translator must be used anywhere a signal passes from one domain to the other.

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    The level shifter at the output of the VCO is especially problematic because it must pass a very wide range of frequencies. When the VCO is starting up, it will produce very low frequencies in the Hz range. As the loop begins to lock, the frequency will quickly rise into the GHz range.

    The main idea of this disclosure is to combine a low- and high-speed level shifter into one design to give a wide frequency range of operation. Low-speed level shifters do well translating voltage from DC to about 500MHz but are not able to pass frequencies above that. High-speed level shifters such as the ac-coupled example shown in Figure 2 do well at passing GHz signals but are not able to pass frequencies in the low MHz range. One characteristic of the ac-coupled level shifter is that when the lower part of it's frequency range is exceeded, voltage peaking after the capacitor occurs (node C in Figure 2). The waveforms in Figure 3 below demonstrate peaking on node c for a low frequency signal, whereas Figure 4 shows the same nodes with no peaking for a 1GHz signal. Detection of the voltage peaking may be used to select the appropriate level translation circuit thereby extending the level translation frequency range of the overall system. If the peaking condition is present, a low-speed level shifter is selected; otherwise, a high-speed level shifter is selected.

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