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Method and System for Fabricating an On-Chip Twisted Pair Interconnect with Multiple Metal Layers

IP.com Disclosure Number: IPCOM000200728D
Publication Date: 2010-Oct-26
Document File: 6 page(s) / 279K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for fabricating an on-chip twisted pair interconnect with multiple metal layers is disclosed.

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Method and System for Fabricating an On

Method and System for Fabricating an OnMethod and System for Fabricating an On -

Multiple Metal Layers

Multiple Metal LayersMultiple Metal Layers

Disclosed is a method and system for fabricating an on-chip twisted pair interconnect

with multiple metal layers. Fig. 1 illustrates an on-chip twisted pair interconnect with

two metal layers and metal vias.

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Figure 1

As depicted in fig.1, based on distance from ground, a width W1 of metal layer 2, a

width W2 of metal layer 1 and a distance "d" between two adjacent strips of the metal

layer 1 is optimized for achieving the same characteristic impedance between two metal layers. This optimization of W1, W2 and d further results in reduced insertion losses. In addition, the on-chip twisted pair interconnect provides maximum noise immunity when driven differentially as any noise coupled into the on-chip twisted pair interconnect generally appears equally on both metal layers in common mode. Moreover, a receiver responds only to the differences in voltage between the metal layers, therefore cross talk between neighboring pairs of interconnects is cancelled.

Fig. 2 illustrates another differential pair structure using metal layer 1 and metal layer 2.

1

Chip Twisted Pair Interconnect with

---Chip Twisted Pair Interconnect with

Chip Twisted Pair Interconnect withChip Twisted Pair Interconnect with


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Figure 2

Fig. 3 illustrates electromagnetic field vector in amperes/meter in metal layers of the on-chip twisted pair interconnect in the presence of neighboring metal line.

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Figure 3

Fig. 4 illustrates near field cross talk of the on-chip twisted pair interconnect.

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Figure 4

Fig. 4 illustrates far field cross talk of the on-chip twisted pair interconnect....