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Method of On-Chip Regulator ESD Protection

IP.com Disclosure Number: IPCOM000200875D
Publication Date: 2010-Oct-27
Document File: 2 page(s) / 50K

Publishing Venue

The IP.com Prior Art Database

Abstract

Aggressive power management, including regulators on-die, became critical part of Application processor IC for mobile products.

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Method of On-Chip Regulator ESD Protection

Abstract

Aggressive power management, including regulators on-die, became critical part of Application processor IC for mobile products.

Introduction

Ø  Modern mobile IC’s requires optimal trade-off between power and frequency performance and this can be done only with on-chip power management, including regulators

Ø  On-chip FET should have very low impedance, that is achieved on account of it’s high size, means area.

Ø  Another critical consideration is ESD protection and thus transistor type selection, that strongly impacts it’s area – high voltage transistor is much more tolerant to ESD, but requires much higher area to get required impedance.

Ø  ESD concern is coming from implementation on-chip regulator with voltage output, routed to IO pads for external bypass capacitor connection. It allows much better stability of regulator.

                                                     Figure 1.

Figure 1 shows pass device of on-die regulator, that is zapped from both terminals.

Proposed solution

Ø  The proposal is to use regulator transistor with low impedance, as actual ESD zap discharge device

Ø  Special circuit on the control of regulator transistor is required to sure it’s open state during ESD event.

Ø  Below is an example of such circuit scheme

Figure 2.

Figure 2 is one of the possible implementations of this proposal.