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Method and System for Measuring Layer to Layer Registration in Printed Circuit Boards

IP.com Disclosure Number: IPCOM000200886D
Publication Date: 2010-Oct-28
Document File: 3 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed to provide a non-destructive electrical measurement technique for measuring layer to layer registration in a printed circuit board by using a time domain reflectometry structure.

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Method and System for Measuring Layer to Layer Registration in Printed Circuit Boards

Disclosed is a method and system for measuring layer to layer registration in a printed circuit board by using a time domain reflectometry structure. The time domain reflectometry structure is a widely available instrument, which is used to determine line impedance. The structures needed for the measurement are a high bandwidth signal launch, and a set of transmission lines sharing a common reference plane.

In order to measure the layer to layer registration between two signal layers, a high speed step signal (edge times <20-30 psec) is launched on one signal layer. After launching the high speed step signal, the time domain reflectometry structure measures the reflected (echo) signals that are received on the other layer. At these edge timings, coupling of energy through openings in reference planes separating two signal layers is sufficient to couple a reverse travelling wave between the signal layers. Measuring the amplitude of the reverse travelling wave determines the degree of registration of the two signal layers in the printed circuit board.

Fig. 1 illustrates a top view and an isometric view of typical wiring in a dense via field under a chip package. Additionally, traces are illustrated on adjacent levels N and N+1. Between the adjacent levels N and N+1, a solid plane of copper is located. This plane acts as a reference plane for the high frequency return signal currents. The reference plane is left intact. However, punchouts, called anti-pads, are required where vias are located to avoid shorting the signals conducted on the vias to the reference planes.

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Figure 1

In case the anti-pads are not present, a stripline structure of reference plane - sign...