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Optimization Aware Clock Skew Scheduling

IP.com Disclosure Number: IPCOM000200966D
Publication Date: 2010-Nov-01
Document File: 5 page(s) / 129K

Publishing Venue

The IP.com Prior Art Database

Abstract

Clock skew scheduling is used in timing critical designs to skew clock in order to meet timing. However if there isn't enough positive slack on the other side of the flop to be skewed, the flop can't be skewed. In many cases the path on the other side of the flop can be optimized further and meet the timing if skewed. This kind of flops can't be skewed by traditional clock skew scheduling algorithms. In this paper a technique is described which looks at scope of further optimization to find such flops and skew them. The advantage is that more flops can be skewed and design can meets its frequency target.

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Document Title

Optimization Aware Clock Skew Scheduling

Abstract 

Clock skew scheduling is used in timing critical designs to skew clock in order to meet timing. However if there isn’t enough positive slack on the other side of the flop to be skewed, the flop can’t be skewed. In many cases the path on the other side of the flop can be optimized further and meet the timing if skewed. This kind of flops can’t be skewed by traditional clock skew scheduling algorithms. In this paper a technique is described which looks at scope of further optimization to find such flops and skew them. The advantage is that more flops can be skewed and design can meets its frequency target.

Body 

During clock skew scheduling attempt is made to skew a flop in order meet timing in a design which has not gone through Clock Tree Synthesis (CTS). This can be done by advancing the clock to startpoint flop or delaying the clock to endpoint flop. The generated skew schedule is passed on the next step, which is CTS to implement the calculated skew schedule. This is done to meet timing frequency target on a design which otherwise can’t meet the target. While generating the clock skews schedule a startpoint flop is checked to see if the slack on input D pin is sufficiently positive so that advancing it by the desired amount won’t cause timing violation on D pin. Similarly an endpoint flop is checked to see if the slack on output Q pin is sufficiently positive so that delaying it by the desired amount won’t cause timing violation on Q pin. If timing slack isn’t sufficiently positive the startpoint or the endpoint flop can’t be skewed. In this case the timing target can’t be met.

In many cases it’s possible that the slack on the other side of flop to be skewed might not be sufficiently positive but it can be optimized to slack positive enough to skew it. This can happen if the logic in the other side of flop is less and during optimization most gates were downsized and/or mapped to high VT cells to gain timing (on other adjoining critical paths) or area or power. If incremental optimization is runs on such paths the slack would increase and it can be skewed. However without running an optimization with high enough +ve slack as the target, these paths can’t be optimized. Even if an optimization is run with such high +ve slack, tools generally won’t be able to optimize all the paths. The paths which were earlier non critical become critical. The opportunity to optimize critical paths by sacrificing timing on non critical paths is lost, so the overall design timing worsens. This would also increase area and power of the design.

In order to be able to skew the kind of flops mentioned above, a new method is being proposed. Instead of optimizing all paths to a good enough positive slack and then doing clock skew scheduling, the clock skew scheduling needs to be aware of the maximum slack that can be achieved in the path and then use this slack to decide if...