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Sharing operand latches between multiple pipelines of a Vector Arithmetic Unit

IP.com Disclosure Number: IPCOM000201023D
Publication Date: 2010-Nov-04
Document File: 4 page(s) / 65K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for sharing operand latches between multiple pipelines of a vector arithmetic unit

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Sharing operand latches between multiple pipelines of a Vector Arithmetic Unit

Disclosed is a method for sharing operand latches between multiple pipelines of a vector arithmetic unit.

In designing processors, it is advantageous to eliminate redundant circuits as the design level. Duplication or redundancy increases the area and poser required for a processor. In a vector floating point unit (FPU) containing multiple multiply-add dataflow macros (MADs) and a permute macro (PRM) which allows data to be communicated between the MADs, a conventional design would have latches in the MADs for the MADs' operands, latches in PRM for the PRM's operands, and muxes before all the operand latches to choose from multiple sources for these operands. MAD and PRM instructions have the same set of possible sources which must be connected to both MAD and PRM muxes, but the FPU does not start a MAD and a PRM instruction in the same cycle. Therefore, the duplication of muxes and latches in both MADs and PRM is redundant, since only one set needs to be active at a time. Since most of the operand bits going to PRM are non-critical, it is not necessary for the PRM operands to be latched in PRM. It saves area, wiring between MADs and PRM, and power to locate shared muxes and latches for all units in the MADs.

The disclosed design takes advantage of cases where the PERM and MADD units do not use these MUX and latches simultaneously. In this case, one set of MUXs and latches are used for both units. In cases where there are potential resource conflicts this approach is not used.

The method takes advantage of shared inputs by combining multiple inputs (MUXs) and latches from both units.

Figure 1 shows the duplication in the multiple units, a conventional design with a separate set of MUXs and latches in macro, where "0DAM" is just a mirror image of "MAD0", FPR is a "floating-point register", A...