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Method to improve stress liner fill profile and avoid void formation

IP.com Disclosure Number: IPCOM000201103D
Publication Date: 2010-Nov-08
Document File: 1 page(s) / 20K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for improving the stress liner fill profile and avoid W subway defect formation in both tensile and compressive stress liners. The method includes a thin stress liner deposition and then sputtering to create a better stress liner profile.

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Method to improve stress liner fill profile and avoid void formation

As Si MOSFET scales, the device pitch becomes smaller. Hence the stress liner fill becomes more difficult, which leads to void formation and then Tungsten subway defect formation. This is a significant yield detractor.

Currently there are no known solutions for this problem.

The dep-etch-dep method would help only on tensile stress liner but the wet clean required creates a surface oxide layer which makes the tensile liner etch harder. The proposed method helps improving the stress liner fill profile and avoid W subway defect formation.

The proposed method includes a thin stress liner deposition and then sputtering to create a better stress liner profile especially on sidewall and fill the void. The second stress liner is then deposited to provide the required stress. This method does not create any surface oxide which is good for stress liner removal in dual stress liner process. It is also a universal approach which can be utilized for both tensile and compressive stress liners.

The process involves:
1. Depositing a thin layer of tensile or compressive stress liner (100A) (no void formation)

2. Sputtering (Ar/N plasma) process to trim the profile and fill the void. The sidewall profile of the nitride liner is improved during the sputtering process which should help improving stress liner fill.

Note: optimize the sputtering process to avoid damaging the spacer

3. Depositing a second stress line...