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use of n+ doped gates to enable defect free replacement metal gate stacks

IP.com Disclosure Number: IPCOM000201139D
Publication Date: 2010-Nov-09
Document File: 1 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a method to prevent defects in metal gate stacks using n+ doped gates to compensate for Boron shadowing.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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use of n+ doped gates to enable defect free replacement metal gate stacks

With tighter pitch, implant shadowing from halo causes the incorporation of different amounts of Boron (B) in the gate stack; therefore, when engineers perform gate silicon removal, B-incorporated regions are not readily etched by wet etch. These becomes defect sites, since the replacement metal gate may not be fill properly, and could manifest in an SRAM as a single cell fail.

To prevent this, the starting gate material is n+ doped to compensate for all the B shadowing. The n+ doped gates enable replacement metal gate silicon removal.

The process for implementing this method is as follows:
1. Gate stack Si deposition
2. Perform As or P implant or incorporate As in the gate stack through a series of ASG + CAP TEOS dep and drive in anneals. For the implant case, there could be CAP TEOS. ASG + TEOS CAP drive-in is a standard process to drive AS in DT to form the plate capacitor.

3. After gate RIE of the n+ gate, standard flow is done up through RMG, where the ammonia/TMAH is now etching uniform n+ gate silicon

4. Any B implanted in the gate from shadowing is compensated by the AS or P in the stack.

This helps with full removal of the gate stack SI and hence could minimize SCF.

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