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Method And System For Determination Of The Execution Of Compare And Swap Instruction

IP.com Disclosure Number: IPCOM000201281D
Publication Date: 2010-Nov-09
Document File: 2 page(s) / 16K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for determining successful execution of ‘Compare and Swap’ (CS) instruction in a computing architecture.

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Method And System For Determination Of The Execution Of Compare And Swap Instruction

Disclosed is a method and system for determining successful execution of 'Compare and Swap' (CS) instruction in a computing architecture. The determination may be performed when the execution of the instruction is interrupted by an asynchronous cancel or other similar event that is beyond the control of the execution program. The determination may also be performed for similar instructions such as, Compare Double and Swap (CDS) and the 64-bit equivalents of the 32-bit CS instructions (CSG, CDSG).

In order to determine the successful execution of a CS instruction, the method and system disclosed herein uses the following algorithm:

A tracking area is initialized in storage to zero.

A non-zero value is set in a general purpose register to

instruction for which the determination is being performed.

An instruction is used to set the Condition Code

Word (PSW). For example, an instruction 'AND Register (NR Rx, Rx)', sets CC = 1 if the content of the register is non-zero. The content of the register will not be changed by the NR instruction.

The content of the register that was the target of the NR instruction is stored into


4.

the tracking area. The storing of the content of the register does not change the Condition Code.

Additionally, any action in the computing architecture that will

not result in a partial update of the storage as seen from another processor could perform the same function as storing the value that is in the register.

Further, the CS event is performed and the Condition Code is set in the PSW to

0 (CC = 0) if the CS instruction is successful and 1 (CC = 1) if the CS instruction is not successful. In case the CS instruction is not successful, the CS event is retried until the CS instruction is successful. To perform the CS event, the current value of the storage being updated by CS instruction is set in a register and a label is designated for retry in the event of a failed CS instruction. Thereafter, the updated value is set in a different register and the CS instruction is executed. If the CS instruction fails, the CS event is retried by branching to retry label designated for the CS instruction and this sequence is repeated until successful.

An indicator in the...