Browse Prior Art Database

FUSE PROGRAMMABLE Dedicated Pins to Dedicated-function I/O Pins CONVERSION

IP.com Disclosure Number: IPCOM000201496D
Publication Date: 2010-Nov-12
Document File: 5 page(s) / 97K

Publishing Venue

The IP.com Prior Art Database

Abstract

More different interfaces to be supported PCI, PCIx, DDR2, QDR2, DDR3, LVDS, etc. ■ More multiple of same interface to be supported System level multi-tasking/processing ■ More # of transceiver channels

This text was extracted from a Microsoft PowerPoint presentation.
This is the abbreviated version, containing approximately 83% of the total text.

Slide 1 of 5

FUSE PROGRAMMABLE Dedicated Pins to Dedicated-function/I/O Pins CONVERSION


Slide 2 of 5

Current & Future Issue

As technology advances

 

USERS demands more I/O pins

FPGA manufacturers face more challenges

■ More different interfaces to be supported

  PCI, PCIx, DDR2, QDR2, DDR3, LVDS, etc.

■ More multiple of same interface to be supported

  System level multi-tasking/processing

■ More # of transceiver channels

■ On-die routing layers cost

■ On-package routing layers cost

■ Package cost

More dedicated configuration pins

  More configuration schemes

■ More test pins

  Higher density device

  More features to be tested

  Less test time (cost reduction)

  Test speed hits limit

   Tester & DFT cost dependent

■ More different level power supply pins

  Support old/new standards, LV-shifter, PD, ...

■ More same level power supply pins

  IR-drop, supply response, jitter reduction

Limited # of user I/O pins

 

2


Slide 3 of 5

PROBLEM SOLVED

■ If interested, user has option to converting [configuration dedicated] pins to [dedicated-func/I/O] pins using exiting FUSE technology

  ● The new-invention implementation still allows user to undo (a few times)

   No prior-art.

   Traditional use of FUSE is only one-time programmable.

3


Slide 4 of 5

WHY

 

(see back up)

■ Device has 16 Dedicated pins just for different configuration modes

  ● JTAG

  ● Active

   Serial

   Parallel

  ● Passive

   Serial

   Parallel

■ Most user uses only 1 of the modes

  Unused dedicated pins are required to tie to...