Browse Prior Art Database

Method of Achieving Minimal Skew Across Multiple Transmit Channels of A Transceiver

IP.com Disclosure Number: IPCOM000201498D
Publication Date: 2010-Nov-12
Document File: 4 page(s) / 68K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention assumes the existence of multiple groups of HSSI channels, where each group is controlled by a common PLL running at a known frequency. This invention uses an extra PLL in the PLD core to generate a series of clocks, stepping through 32 possible phases of one parallel clock cycle. Separate phase detection circuits compare this sweeping clock to the phase of clocks associated with each group of channels, and determines which phase of the common PLL is the best match. Using this data, an alignment circuit adjusts the data to be transmitted to compensate for the phase variance that will be introduced by the transmission.

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Problem Solved:

This invention describes a method to minimize the transmission skew between multiple channels of CDR data, when the number of channels exceeds the reach of available low-skew clock distribution lines.

Prior Art

Devices provide dedicated resources to minimize channel to channel skew.  Examples of these resources include quad-to-quad clock lines, and multi-quad “xN” lines.  For data rates above 6.5Gbps, only groups of four channels can be supported.  For larger groups, the maximum data rate can be as low as 3.25Gbps. 

Therefore, groups of channels that are larger than the maximum collection for a given data rate cannot be bonded together.  The skew between channels is then a function of the serialization factor and whether the byte serializer is used. 

Brief Description of Invention

This invention assumes the existence of multiple groups of HSSI channels, where each group is controlled by a common PLL running at a known frequency.  This invention uses an extra PLL in the PLD core to generate a series of clocks, stepping through 32 possible phases of one parallel clock cycle.  Separate phase detection circuits compare this sweeping clock to the phase of clocks associated with each group of channels, and determines which phase of the common PLL is the best match.  Using this data, an alignment circuit adjusts the data to be transmitted to compensate for the phase variance that will be introduced by the transmission.  

Benefits / Advantages

This invention achieves a total skew of 3 UI across the group of channels, down from as high as 50 UI in the case of 16-bit serialization with a byte serializer.

Detailed description

Problem:  We have multiple groups of channels.  Each group of channels (one quad) has a PLL generating the clock for the channels.  Therefore, each PLL can have a different phase from the other PLLs.

Problem:  Given a common source clock, multiple channels make independent phase decisions.  A given channel may make a different decision after each reset. 

Problem:  We have a FIFO to make successful transfers from the PLD fabric to the HSSI channel.  This FIFO has read and write pointers that can start at different offsets after each reset.  This introduces skew from channel to channel

Problem:  The clock that is the reference for the PLLs has a different arrival time at each PLL, due to differences in routing delay

Describe the invention.

Put the quads are in x4 mode, which reduces skew within a quad.  Have each quad contribute a reference clock to a phase detection circuit.  Use a core PLL to sweep through potential clock phases and figure out which of 32 phases is the best match to the quad’s reference clock.  Using that information, drive a bitslip circuit to pre-slip the data going to each TX channel.

Other solutions we considered

Original (pre-2009): Use quad-level bonding, with a xN line to distribute Gen1/Gen2/Gen3 clock across all 16 channels from a common pair of CMU PLLs.  Thi...