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Method and System for Extracting Width Offset For Thick and Thin Gate-Oxide Devices

IP.com Disclosure Number: IPCOM000201535D
Publication Date: 2010-Nov-15
Document File: 2 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for extracting width offset for thick and thin gate-oxide devices is disclosed.

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Method and System for Extracting Width Offset For Thick and Thin Gate -Oxide Devices

Disclosed is a method and system for extracting width offset for thick and thin gate oxide devices. Further, the method and system disclosed herein describes how the width offset is dependent on length for thick and thin oxide devices.

Body contacted (BC) devices in Silicon-on-Insulator (SOI) technology have additional width due to the special layout needed to contact body nodes of these devices. The additional width is termed as width offset. Therefore, the total effective width of these devices depends on the width offset.

The method and system disclosed herein extracts the width offset for thick gate-oxide devices by comparing linear currents of floating body (FB) and body contacted (BC) devices which have the same dimensions. Exemplarily, the width offset may correspond to the "Width offset for Body-contact Isolation Edge" (dwbc) parameter in a Berkeley Short-channel IGFET Model Silicon on Insulator (BSIMSOI) model. On comparing the linear currents, the width offset is determined by measuring the difference between the FB and the BC linear currents. The extra current in BC devices comes due to the width offset and is used to extract the width offset for thick gate-oxide devices based on the following equations. Here, the linear currents are compared to avoid any floating body effects.

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