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Method and System for Placement of Spare Circuitry in an Integrated Circuit Design

IP.com Disclosure Number: IPCOM000201541D
Publication Date: 2010-Nov-15
Document File: 6 page(s) / 433K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for placing spare circuitry in an integrated circuit (IC) design is disclosed. The disclosed method and system enable distribution of the spare circuitry such that, the spare circuitry is accessible in an event of Engineering Change Order (ECO).

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This is the abbreviated version, containing approximately 45% of the total text.

Page 01 of 6

Method and System for Placement of Spare Circuitry in an Integrated Circuit Design

Disclosed is a method and system for placing spare circuitry in an integrated circuit (IC) design. Placement of the spare circuitry, such as spare latches, is done based on area utilization of a main logic and placement of Local Clock Buffers (LCBs) on the IC design. The method involves distribution and placement of a set of spare latches (S), such that availability of these spare latches is enhanced in Engineering Change Order (ECO) prone segments. To accomplish this, subsets (n) of the set of spare latches are determined in a manner that conditions illustrated in equation 1 and equation 2 are met.

n

S

=

U

S

i

i

1

=

(1)

n

I

S

{ }

i

=

φ

=1 (2)

Based on the equation 1 and equation 2, a collection of all spare latches in different subsets should yield the spare latches in whole IC design and one spare latch should exist in only one subset.

A flowchart illustrating the disclosed method is shown in Fig. 1 and Fig. 2.

i

1


Page 02 of 6

(This page contains 00 pictures or other non-text object)

Figure 1

2


Page 03 of 6

(This page contains 00 pictures or other non-text object)

Figure 2

The method involves determination of number of spare latches in each subset of the set of spare latches. This involves allocating the spare latches (P) to a segment of the IC design on basis of utilization and number of LCBs in the segment. Further, cardinality or number of spare latches (Ci) of a subset (Si) is determined on basis of a relative weight assigned to the segment. The relative weight is evaluated based on normalized area utilization (LWUi) and normalized LCB count (LCUi) for each segment of the IC design, and are given based on equation 3 and equation 4.

n

to

i

quadrant

the

of

area

Total

quadrant

Total

LWUi 1

;

=

area

of

the

ins

tan =

ces

in

a

(3)

3


Page 04 of 6

Total

LCUi 1

;

number

of

LCBs

in

a

quadrant

i

to

n

=Total

number

of

LCBs

in

the

de

sin =

(4)

The relative weight for each segment of the IC design is determined by giving equal importance to each of these normalized factors and is obtained by computing an average of the normalized area utilization (LWUi) and the normalized LCB count as given in equation 5.

n

to

i

L

+

=

L2 =

;

(5)

Upon determination of the relative weights, number of spare latches in each segment of the IC design is determined. This involves dividing total design area into 4 segments,
i.e. n = 4 and assigning the spare latches to these segments. Initially, at least one spare latch is assigned to each segment, if there is at least one LCB in that segment and the number of spare latches in the IC design is more than four. However, if the number of spare latches in the IC design is less than four then they are assigned on the basis of relative weight. This step increases the probability of assignment of at least
one spare latch to every LCB. QINITIALjin equation 6 represents the initial number of spare latches assigned to the segm...