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Method and System for Functional Validation of Multicore Processors with an Integrated Self-Generating Testcase Framework

IP.com Disclosure Number: IPCOM000201550D
Publication Date: 2010-Nov-15
Document File: 6 page(s) / 200K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for functional validation of multicore processors with an integrated self-generating testcase framework is disclosed. Pools of self-generating test cases help in eliminating long test cases build times in the multicore processors systems.

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Method and System for Functional Validation of Multicore Processors with an Integrated Self-Generating Testcase Framework

Disclosed is a method and system for functional verification or validation of multicore processors with an integrated self-generating testcase framework thereby eliminating long test cases build times in the multicore processors systems.

Typically, functional verification of execution units of a processor involves verification of various group of instructions implemented in the processor. The group of instructions is huge therefore it is practically not feasible to verify all the instructions with various possible inputs in a pseudo random way. Therefore, the method and system groups these instructions based on an instruction format. The instructions belonging to a similar instruction format are grouped together and a table is built based on this grouping of instructions. The instruction grouping table is shown in Fig. 1. Such grouping of instruction facilitates in replacing an instruction belonging to a group by any other instruction belonging to the similar group. As depicted in the Fig. 1, OR Mask in the table includes information regarding an opcode and an extended opcode of a particular instruction.

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Figure 1

In an instance, another module namely a test program generator builds a test program. During this process of building the test program, all the information related to the current test program is stored into a test program information table. The test program information table is shown in Fig. 2.

As depicted in Fig. 2, the test program information table contains 'n' number of test cases labeled Test case 1 to Test case n. Various information associated with these test cases include an address of instructions in the test cases, a group to which an instruction belongs, and an AND mask of the instructions i.e. bits that may not be changed in an instruction word. This information is stored in a proper format as shown in Fig. 2.

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Figure 2

Thereafter, the instruction grouping table (shown in Fig. 1) and the test program information table (shown in Fig. 2) are used for self-generating test cases. This self-generation code is added as a part of an interrupt handler routine. Fig. 3 depicts the flow chart of self-generating test cases.

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Figure 3

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Initially a test case other than the one that is currently under execution, which needs to be regenerated is identified. A "Next to execute" flag is set for the testcase which is picked for re-generation. Thereafter, the corresponding test case information is fetched from the test program information table. The test program information table also provides a base address of various groups of instructions. Subsequently, all the addresses are traversed based on an instruction co...