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Method and System for Verification of Controlled Clock Gating in Multi-Clock Domain

IP.com Disclosure Number: IPCOM000201572D
Publication Date: 2010-Nov-15
Document File: 1 page(s) / 19K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for verification of controlled clock gating in multi-clock domain is disclosed. The verification of controlled clock gating in multi-clock domain is performed during simulation to improve simulation speed and reduce the consumption disk space.

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Method and System for Verification of Controlled Clock Gating in Multi -Clock Domain

In general, with the increasing complexity and size of System-on-Chip (SOC), more complicated cores such as, multiple Peripheral Component Interconnect (PCI) Express IP cores are added as part of SOC. Because of this, simulation time is drastically increased and more cycles are required to complete a verification process of the SOC. Hardware accelerators are used to reduce the simulation time. However, the hardware accelerators may require different simulation environment and programming codes. As a result, the use of hardware accelerators proves to be expensive. In addition, not all IP cores are feasible for verification in this environment.

In order to overcome this problem, a method and system is disclosed for verification of controlled clock gating in multi-clock domain.

In a typical multiple-clock domain simulation, all fast and slow clocks are active at system reset. As such, some of the slow-speed devices, such as serial Read Only Memory (ROM), are used to load critical system setup data. During this process, the rest of the devices are inactive while initial system data is being read. In logic simulation, an event-based simulator always evaluates changing events of multiple clocks. As a result, the event-based simulator significantly adds up simulation time during system reset and initial system configuration data transfer by slow-speed devices. In the present method, cl...