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Efficient global carry scheme in (hierarchical implementation of) wide prefix adder design

IP.com Disclosure Number: IPCOM000201573D
Publication Date: 2010-Nov-15
Document File: 3 page(s) / 103K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for optimizing global carry in wide parallel prefix adder design

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Efficient global carry scheme in (hierarchical implementation of ) wide prefix adder design

Disclosed is a method for optimizing global carry in wide parallel prefix adder design.

In microprocessor designs, adders are expected to be on critical paths. To speed up, fast adders are typically designed mixing parallel prefix adders with carry-select scheme.

As illustrated in Figure 1, the partial sums (S0, S1) and group-carries (C0, C1)

                                                                                are pre-computed and then merged in the last stage with actual carry-in in conventional fast adder designs. The circuit redundancy increases area and power cost in the design. For this reason, reducing the overall cost of adders, should improve any microprocessor.

In designing processors, it is advantageous to eliminate redundant circuits at the design level. Utilizing a hierarchical design for wide adders allows for taking advantage of hierarchical prefixes to manipulate late-arrival carry-in signal. Carry

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                                                                       in is merged into group prefix computation. This early merging speeds up carry propagation without compromising late-arrival carry

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                                                                             in. This approach is shown in Figure 2 and Figure 3 below. In Figure 2, the design offers equivalent speed performance as the conventional design in Figure 1 without requiring redundant circuitry for S0/S1, C0/C1, saving area and power as result. In Figure 3, the design improve the performance by one delay stage at the same cost as in Figure 1.

Figure 1 is an example of a conventional wide prefix adder design mixing with carry-select scheme, redundant circuitry is required.

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Figure 1

.Figure 2 is an example of a new design, with equivalent timing but less area/power than conventional scheme in Figure 1.

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Figure 2

Figure 3 is an example design with equivalent circuitry but faster speed than conventional...