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Method and System for Maintaining a Central Electronic Complex (CEC) Model during Maintenance Operations

IP.com Disclosure Number: IPCOM000201575D
Publication Date: 2010-Nov-15
Document File: 2 page(s) / 20K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for maintaining a Central Electronic Complex (CEC) model during maintenance operations is disclosed. The CEC model represents a real-time hardware configuration of a CEC during a maintenance operation.

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Method and System for Maintaining a Central Electronic Complex (CEC) Model during Maintenance Operations

Disclosed is a method and system for maintaining a Central Electronic Complex (CEC) model during maintenance operations. The CEC model represents a real-time hardware configuration of a CEC during a maintenance operation.

During a maintenance operation, such as a CEC Concurrent Maintenance (CCM) operation, a failure may occur, which is rectified using an operation such as a Flexible Service Processor (FSP) recovery and redundancy or data capture operations. Accordingly, the method and system disclosed herein rebuilds an existing CEC model, subsequent to the execution of the rectification operation. In an instance, the CEC model is a Hardware Object Model (HOM) representing a hardware configuration of the CEC. Accordingly, when the hardware configuration of the CEC is modified, the CEC model is altered and updated to account for any new hardware components. Further, the method and system leverages existing Recovery, Availability, and Serviceability (RAS) recovery features of the CEC during the CCM operations. RAS features of the CEC includes redundancy, recovery and failure data capture features, such as redundant FSPs, reset or reload, and platform and hardware unit dump.

In order to handle these RAS recovery features in a CCM operation, the HOM is updated with the new hardware configuration based on a state of the CEC prior to the execution of RAS recovery features. In order to accomplish this, the HOM is populated in an area P1 of a persistent memory. P1 persists any resets or reloads but ignores hard FSP resets. Further, another area P0 is maintained in the persistent memory which is not subjected to any resets or reloads.

For example, an algorithm for maintaining a HOM in the persistent memory during addition of a hardware com...