Browse Prior Art Database

Fault detection and isolation of machine constants

IP.com Disclosure Number: IPCOM000201592D
Publication Date: 2010-Nov-15
Document File: 3 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention demonstrates a novel approach to detection of machine faults that are traditionally not testable in the realm of machine configuration and other internal machine constants. The new approach also incorporates error detection and reporting as well in a running system.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 3

Fault detection and isolation of machine constants

Disclosed is a design that enables manufacturing test and reliability monitoring of machine configuration, timing and repair constants in a microprocessor. Current design practices utilize thousands of such constants with down stream fault detection that is implicit at best when the machine operates erratically. In this new design, test coverage is improved and error checking is enabled to flag an error if unexpected state changes occur in the operational system.

The crux of the invention is to add scannable observation latches at each destination which would clock during one of three times. This latch would be scannable in the same context as the configuration latch so that a standard deterministic stuck fault test could be applied to directly detect manufacturing defects on these latches and buffer trees. It would also be clocking during logic built in self test so a misr signature derived from the repaired and configured chip could be evaluated at boot time to make sure no faults arose in this critical control function. There is a third operational mode in which this circuit is placed in an error detect mode. This last mode could be used to set an error bit in the event of a state change in the constant being observed.

In current processor design there are countless examples of a single processor being used to cover multiple configurations of buses and modes of operation. It is typical for the enabling/disabling of buses or features is governed by an initial load of simple scan only latches where the clock is only active during a reset operation and the value is expected to remain fixed thereafter. This results in a sequential process of setting machine state until the desired configuration is set.

Other programmable features that are increasingly be adopted are localized timing controls that can adjust basic characteristics of clock waveform at a level as specific as a group of 20 latches. In the course of technology development new settings are often learned and applied at machine boot time.

The last set of machine constants introduced for this discussion are latch settings that govern the repair of defective areas in on chip arrays and caches. Methods in place today afford the derivation of new repairs each time the machine is booted in the extreme case.

While these constants are by no means the only ones present in a current processor, these are examples of the ones that share th...