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Method and System for Generating Test cases for Verifying Microprocessors for Pre-Silicon Environment

IP.com Disclosure Number: IPCOM000201729D
Publication Date: 2010-Nov-19
Document File: 4 page(s) / 128K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is provided to generate test cases for verifying microprocessors in a pre-silicon environment. An abstract test case, an Instruction Regeneration Table, and a Register Shuffling Table are generated for a simulation environment. Simulation results are generated for the test cases and bundled along with the abstract test case. Real test cases are then generated and executed. The results of the real test cases are compared to the simulation results in a target pre-silicon environment.

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Method and System for Generating Test cases for Verifying Microprocessors for Pre -Silicon Environment

Disclosed is a method and system for generating test cases for verifying microprocessors in a pre-silicon environment, such as AWAN* environment.

In an instance, simulation test results are generated using a simulation environment. An abstract test case, an Instruction Regeneration Table, and a Register Shuffling Table are generated for the simulation environment. The Instruction Regeneration Table and the Register Shuffling Table are generated using a Run-Time Execution (RTX) manager. Further, a base kernel running in the simulation environment generates different combinations of test cases with different input values using the Instruction Regeneration Table and the Register Shuffling Table. Thereafter, the simulation results generated for the test cases are bundled along with the abstract test case and the Instruction Regeneration Table. In an instance, the Cyclic Redundancy Check (CRC) values of the simulation results are used in order to lower the size of an image created for the simulation environment. The Instruction Regeneration Table contains information used for generating real test cases from abstract test cases. Real test cases are then executed for verifying the microprocessors and the results of the test cases are compared to the CRC values of the simulation results in the target pre-silicon environment.

Fig. 1 illustrates a flow diagram depicting the generation of the abstract test case, the Instruction Regeneration Table, the Register Shuffling Table, and the CRC values of the simulation results. An exemplary screenshot of an abstract test case generated by the RTX manager is shown in Fig. 2.

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Figure 1

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Figure 2

Fig. 3 exemplarily illustrates an Instruction Regeneration Table used for building test cases in the pre-silicon environment. The Instruction Regeneration Table contains information used for generating real test cases from abstract test cases. Column "1" of the Instruction Regeneration Table contains pass/address of abstract test cases while Column "2" contains the Group corresponding to the abstract test cases. Further, Column "3" to Column "n" of the Instruction Regeneration Table contains details needed to generate a real test case. In this case, the real test case is "Opcode" or "Xopcode". The size of the Instruction Regeneration Table small since it contains minimal data to generate a real test case.

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Figure 3

The Instruction Regeneration Table allows creating new instructions for passes and the Register Shuffling Table allows generati...