Browse Prior Art Database

Exclusive mode bits for static timing analysis.

IP.com Disclosure Number: IPCOM000201792D
Publication Date: 2010-Nov-23
Document File: 3 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a technique for dealing with static timing analysis of false paths. A new tool feature is introduced which allows the user to give the timing tools information regarding paths that are mutually exclusive and should not be timed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 55% of the total text.

Page 01 of 3

It is not uncommon to have situations where timing paths are shown by the timing tool model which cannot physically occur. Two examples are illustrated in the Figure 1 below. In the top part of the figure, data from a latch labeled L1 is captured by a latch labeled L3. The clocks to both latches are fed by a mux which selects either Clock1 or Clock2. Because of the mux, it may not be appropriate to time tests between the two clocks at latch L3. However, the timing tools do not understand this situation properly. Another situation is illustrated in the bottom of the figure where the path through these muxes cannot logically happen. The timing tools also cannot detect this situation and will try to time this path.

    For the first example, it is possible to properly model the situation by creating new clock phase names at the mux and declaring them to be mutually exclusive. The drawback of this approach is that the user needs to manually identify each mux and create new sets of clock phases for each of the muxes.

    For the second example, it is possible to mask the path with false path assertions, but it can be tedious to correctly identify the paths and code the assertions such that only the false path is masked an no valid paths are masked.

L1

L5 L6

Ȉˇ ˄ ˙ ˝

    The invention is to create a new command to allow the user to specify pins or nets which are used as exclusive mode bits. Logic gates connected to those mode bits will have special tags added to the clock phase tags which arrive there. This will be described in more detail below.

    This approach has the advantage of being simple for the end user. It reduces the chance of escapes in coverage due to errors in assertion coding. The invention includes an added command for the static timing tool and a software algorithm associated with the command.

1

Clock1

Clock2

D

C

0

1

D

C

L3

Mode bit

invert

0

1

D

C

D

C

0

1


Page 02 of 3

    The steps of operation are described by the following steps and illustrated in Figure 2 below.
1) User uses a new command "set

_exclusive

_mode

_bit

-pin "Mode bit".
2) The mode bit is assigned a unique numeric mode identifier (referred to as the MID).
3) The timing tool traces forward (through any buffers or inverters) from the mode bit signal to any connected logic gates.
a. Any inversions in the fanout tree are handled by using a + or - flag on...